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参数资料
| 型号： | CD40100BDMSR |
| 厂商： | INTERSIL CORP |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | 32-BIT BIDIRECTIONAL SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16 |
| 封装： | BRAZE SEALED, CERAMIC, DIP-16 |
| 文件页数： | 1/9页 |
| 文件大小： | 65K |
| 代理商： | CD40100BDMSR |
7-1277
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright
Intersil Corporation 1999
CD40100BMS
CMOS 32-Stage Static
Left/Right Shift Register
Description
CD40100BMS is a 32-Stage shift register containing 32
D-type master-slave ip-ops.
The data present at the SHIFT RIGHT INPUT is transferred
into the rst register stage synchronously with the positive
CLOCK edge, provided the LEFT/RIGHT CONTROL is at a
low level, the RECIRCULATE CONTROL is at a high level,
and the CLOCK INHIBIT is low. If the LEFT/RIGHT
CONTROL is at a high level and the RECIRCULATE
CONTROL is also high, data at the SHIFT LEFT INPUT is
transferred into the 32nd register stage synchronously with
the positive CLOCK transition, provided the CLOCK INHIBIT
is
low.
The
state
of
the
LEFT/RIGHT
CONTROL,
RECIRCULATE CONTROL, and CLOCK INHIBIT should not
be changed when the CLOCK is high.
Data is shifted one stage left or one stage right depending on
the state of the LEFT/RIGHT CONTROL, synchronously with
the positive CLOCK edge. Data clocked into the rst or 32nd
register states is available at the SHIFT LEFT or SHIFT
RIGHT OUTPUT respectively, on the next negative CLOCK
transition (see Data Transfer Table). No shifting occurs on the
positive CLOCK edge if the CLOCK INHIBIT line is at a high
level. With the RECIRCULATE CONTROL low, data in the
32nd stage is shifted into the rst stage when the LEFT/
RIGHT CONTROL is low and from the rst stage to the 32nd
stage when the LEFT/RIGHT CONTROL is low, and from the
rst state to the 32nd stage when the LEFT/RIGHT control is
high. The CD40100BMS is supplied in these 16-lead outline
packages:
Braze Seal DIP
H4T
Frit Seal DIP
H2R
Ceramic Flatpack
H6W
Features
High Voltage Type (20V Rating)
Fully Static Operation
Shift Left/Shift Right Capability
Multiple Package Cascading
Recirculate Capability
LIFO of FIFO Capability
100% Tested for Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Maximum Input Current of 1
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Standardized, Symmetrical Output Characteristics
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specications for Description of
‘B’ Series CMOS Devices”
Applications
Serial Shift Registers
Time Delay Circuits
Expandable N-Bit Data Storage Stack (LIFO Operation)
December 1992
File Number
3349
Pinout
CD40100BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
NC
CLOCK INHIBIT
CLOCK
SHIFT LEFT OUT
NC
SHIFT LEFT IN
VSS
NC
VDD
NC
LEFT/RIGHT
SHIFT RIGHT OUT
SHIFT RIGHT IN
NC
RECIRCULATE
NC
CONTROL
NC = NO CONNECTION
Functional Diagram
VSS = 8
VDD = 16
SHIFT RIGHT
4
2
9
13
SHIFT RIGHT
12
OUT
CLOCK INHIBIT
SHIFT LEFT
6
CLOCK
11
SHIFT LEFT
4
OUT
RECIRCULATE
CONTROL
IN
LEFT/RIGHT
CONTROL
NC = 1, 5, 7, 10, 14, 15
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CD40100BF/3 | 制造商:Harris Corporation 功能描述: |
| CD40100BMS | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CMOS 32-Stage Static Left/Right Shift Register |
| CD40101BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CD40101BFS2225 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40101BFX | 制造商:Harris Corporation 功能描述: |
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