参数资料
型号: CDB4365
厂商: Cirrus Logic Inc
文件页数: 37/52页
文件大小: 0K
描述: EVALUATION BOARD FOR CS4365
标准包装: 1
DAC 的数量: 6
位数: 24
采样率(每秒): 192k
数据接口: 串行
DAC 型: 电压
工作温度: -40°C ~ 85°C
已供物品: 板,缆线,CD
已用 IC / 零件: CS4365
相关产品: CS4365-DQZR-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP
CS4365-DQZ-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP
598-1060-ND - IC DAC 6CH 114DB 192KHZ 48LQFP
其它名称: 598-1779
CS4365
6.4.2 Direct DSD Conversion (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode, the full-scale DSD and PCM levels will not be matched (see Section ), the dynamic range
performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available
(see Section for filter specifications).
6.4.3 Static DSD Detect (STATIC_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
6.4.4 Invalid DSD Detect (INVALID_DSD)
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
6.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE)
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation
Mode. (See Figure 18 on page 27 )
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.
6.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN)
Function:
When set to 1, DSD phase modulation input mode is enabled, and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
DS670F2
37
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