参数资料
型号: CDB4365
厂商: Cirrus Logic Inc
文件页数: 7/52页
文件大小: 0K
描述: EVALUATION BOARD FOR CS4365
标准包装: 1
DAC 的数量: 6
位数: 24
采样率(每秒): 192k
数据接口: 串行
DAC 型: 电压
工作温度: -40°C ~ 85°C
已供物品: 板,缆线,CD
已用 IC / 零件: CS4365
相关产品: CS4365-DQZR-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP
CS4365-DQZ-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP
598-1060-ND - IC DAC 6CH 114DB 192KHZ 48LQFP
其它名称: 598-1779
CS4365
Pin Name
VQ
FILT+
#
21
20
Pin Description
Quiescent Voltage ( Output ) - Filter connection for internal quiescent voltage. VQ must be
capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nom-
inal voltage level is specified in the Analog Characteristics and Specifications section. VQ pre-
sents an appreciable source impedance and any current drawn from this pin will alter device
performance. However, VQ can be used to bias the analog circuitry assuming there is no AC
signal component and the DC current is less then the maximum specified in the Analog Char-
acteristics and Specifications section.
Positive Voltage Reference ( Output ) - Positive reference voltage for the internal sampling cir-
cuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection
Diagram.
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
39,40
37,38
35,36 Differential Analog Output ( Output ) - The full-scale differential analog output level is specified
33,34 in the Analog Characteristics specification table.
29,30
27,28
MUTEC1
MUTEC2
MUTEC3
MUTEC4
MUTEC5
MUTEC6
41
26
25
24
23
22
Mute Control ( Output ) - The Mute Control pins go high during power-up initialization, reset,
muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. These
pins are intended to be used as a control for external mute circuits on the line outputs to pre-
vent the clicks and pops that can occur in any single supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute minimum in extraneous clicks
and pops.
Hardware Mode Definitions
M0
17
M1
M2
M3
M4
16
15
12
10
Mode Selection ( Input ) - Determines the operational mode of the device as detailed in Table 6
and Table 7 .
Software Mode Definitions
Serial Control Port Clock ( Input ) - Serial clock for the serial control port. Requires an external
SCL/CCLK
SDA/CDIN
AD0/CS
TST
DSD Definitions
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSD_SCLK
DS670F2
15
16
17
10, 12
3
2
1
48
47
46
42
pull-up resistor to the logic interface voltage in I2C ? Mode as shown in the Typical Connection
Diagram.
Serial Control Port Data ( Input/Output ) - SDA is a data I/O line in I2C Mode and is open drain,
requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Con-
nection Diagram; CDIN is the input data line for the control port interface in SPI ? Mode.
Address Bit 0 (I2C) / Control Port Chip Select (SPI) ( Input ) - AD0 is a chip address pin in I2C
Mode; CS is the chip-select signal for SPI Mode.
Test - These pins need to be tied to analog ground.
Direct Stream Digital Input ( Input) - Input for Direct Stream Digital serial audio data. GND if
unused.
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.
7
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