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参数资料
| 型号： | CDB4398 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 16/46页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS4398 DAC |
| 标准包装： | 1 |
| DAC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | I²C，SPI? |
| DAC 型： | 电压 |
| 工作温度： | -10°C ~ 70°C |
| 已供物品： | 板，线缆 |
| 已用 IC / 零件： | CS4398 |
| 产品目录页面： | 757 (CN2011-ZH PDF) |
| 相关产品： | 598-1067-5-ND - IC DAC 120DB 192KHZ W/VC 28TSSOP |
| 其它名称： | 598-1155 |
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DS568F1
23
CS4398
4.6.1
Recommended Power-up Sequence (Stand-Alone Mode)
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control
Port is reset to its default settings.
2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone power-
up sequence following approximately 218 MCLK cycles.
4.7
Control Port Mode
4.7.1
Recommended Power-up Sequence (Control Port Mode)
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control
Port is reset to its default settings.
2. Bring RST high. Set the CPEN bit (Reg. 8h) prior to the completion of the Stand-Alone power-up se-
quence (approximately 218 MCLK cycles). Setting this bit halts the Stand-Alone power-up sequence
and initializes the Control Port to its default settings. The desired register settings can be loaded while
keeping the PDN bit (Reg. 8h) set to 1.
3. Clear the PDN bit to initiate the power-up sequence.
If the CPEN bit is not written within the allotted time, the device will start-up in stand-alone mode and begin
converting data according to the current state of the M0 to M3 pins. Since these pins are also the control
port pins an undesired mode may be entered. For this reason, if the CPEN bit is not set before the allotted
time elapses, the SDIN line must be kept at static 0 (not dithered) until the device is properly configured.
This will keep the device from converting data improperly.
4.7.2
Sample Rate Range/Oversampling Mode (Control Port Mode)
Sample rate mode selection is determined by the FM bits (Reg. 02h).
4.7.3
Serial Audio Interface Formats (Control Port Mode)
The desired serial audio interface format is selected using the DIF2:0 bits (Reg. 02h).
4.7.4
MUTEC Pins (Control Port Mode)
The auto-mute polarity feature (mentioned in Section 4.3) is defeatable. The MUTEP1:0 bits in register
04h give the option to override the mute polarity which was auto detected at startup (see the Register De-
scription section for more details).
4.7.5
Interpolation Filter (Control Port Mode)
To accommodate the increasingly complex requirements of digital audio systems, the CS4398 incorpo-
rates selectable interpolation filters. A fast and a slow roll-off filter are available in each of Single-, Double-
, and Quad-Speed modes. These filters have been designed to accommodate a variety of musical tastes
and styles. The FILT_SEL bit (Reg. 07h) is used to select which filter is used (see the Register Description
section for more details).
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43
in the “Appendix” on page 41.
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