参数资料
型号: CDB4398
厂商: Cirrus Logic Inc
文件页数: 22/46页
文件大小: 0K
描述: BOARD EVAL FOR CS4398 DAC
标准包装: 1
DAC 的数量: 2
位数: 24
采样率(每秒): 192k
数据接口: I²C,SPI?
DAC 型: 电压
工作温度: -10°C ~ 70°C
已供物品: 板,线缆
已用 IC / 零件: CS4398
产品目录页面: 757 (CN2011-ZH PDF)
相关产品: 598-1067-5-ND - IC DAC 120DB 192KHZ W/VC 28TSSOP
其它名称: 598-1155
DS568F1
29
CS4398
7.
REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
7.1
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID, which is 01110b (14h), and the remain-
ing Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
7.2
Mode Control 1 - Register 02h
7.2.1
DSD Input Source Select (DSD_SRC) BIT 7
Function:
When set to 0 (default), the dedicated DSD pins will be the active DSD inputs.
When set to 1, the source for DSD inputs will be as follows:
DSDA input on SDATA pin
DSDB input on LRCK pin
DSD_SCLK input on SCLK pin
The dedicated DSD pins must be tied low while not in use.
7.2.2
Digital Interface Format (DIF2:0) BITs 6-4
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format, and the options are detailed in Figures 3 through 5.
7
6
5
432
10
PART4
PART3
PART2
PART1
PART0
REV2
REV1
REV0
01
11
0
-
7
6
5
432
10
DSD_SRC
DIF2
DIF1
DIF0
DEM1
DEM0
FM1
FM0
00
DIF2
DIF1
DIF0
Description
Format
Figure
000
Left-Justified, up to 24-bit data
0
(Default)
001
IS, up to 24-bit data
010
Right-Justified, 16-bit data
011
Right-Justified, 24-bit data
100
Right-Justified, 20-bit data
101
Right-Justified, 18-bit data
110
Reserved
111
Reserved
Table 5. Digital Interface Formats - PCM Mode
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