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| 型号： | CDB5343 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 6/23页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5343 STEREO ADC |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 108k |
| 数据接口： | 串行 |
| 在以下条件下的电源（标准）： | 60mW @ 5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5343，CS5344 |
| 已供物品： | 板，CD |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | CS5343-DZZR-ND - IC ADC AUD 98DB 108KHZ 10-TSSOP CS5343-CZZR-ND - IC ADC AUD 98DB 108KHZ 10-TSSOP 598-1689-ND - IC ADC AUD 98DB 108KHZ 10TSSOP 598-1189-ND - IC ADC AUD 98DB 108KHZ 10-TSSOP |
| 其它名称： | 598-1156 |
CDB5343
8. CONNECTORS
Table 1 lists the connectors on the CDB5343, the reference designator of each connector, the directionality, and
the associated signal.
REFERENCE
CONNECTOR DESIGNATOR INPUT/OUTPUT
SIGNAL
+5V
GND
AINR
AINL
Co-axial
Optical
I/O HDR
J2
J1
J7
J5
J6
J9
J3
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT/OUTPUT
+5 V power to crystal oscillator and DC voltage regulator
Ground connection from the power supply
Analog input right channel
Analog input left channel
Digital audio (S/PDIF) output
Digital audio (S/PDIF) output
Master Clock, Serial Clock, Left/Right Clock, SDOUT
Table 1. System Connections
9. JUMPER AND SWITCH SETTINGS
The user can fully configure the CDB5343 with a bank of six DIP switches (S1) and a single jumper setting on header
J4.
9.1
9.2
Jumper J4
This jumper selects the magnitude of VA, either 3.3 V or 5 V. The CS5343 is a single-supply device; there-
fore the magnitude of VA affects the full-scale analog input voltage as well as the digital I/O voltage. Digital
I/O is always fixed at VA, and the full-scale input is nominally 0.56xVA Vpp, as specified in the CS5343 data
sheet. If the user selects 5 V, the CS5343 full-scale analog input voltage is 2.82 Vpp (1 Vrms) and the digital
I/O is set to 5 V. If 3.3 V is selected, the full-scale analog input voltage is 1.86 Vpp (660 mVrms) and digital
I/O is 3.3 V.
Switch S1
OPEN
CLOSED
9.2.1
CS5343
CS5343
CS8406
MCLK
SCLK, LRCK
SPEED
MCLK/LRCK
MASTER (default)
MASTER
FROM HDR
FROM HDR
DSM
256x (default)
Table 2. CDB5343 S1 Settings
SLAVE
SLAVE (default)
TO HDR (default)
TO HDR (default)
SSM (default)
384x
This switch configures the CS5343 for either Master Mode or Slave Mode operation. When set as clock
Master, the CS8406 must be set to “Slave” and “SCLK, LRCK” must be set to “TO HDR.” When CS5343
is configured for Slave Mode, the CS8406 must be set for Master Mode, or “SCLK, LRCK” must be set to
“FROM HDR.”
6
DS687DB2
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