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参数资料
| 型号： | CDB5343 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 7/23页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5343 STEREO ADC |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 108k |
| 数据接口： | 串行 |
| 在以下条件下的电源（标准）： | 60mW @ 5V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5343，CS5344 |
| 已供物品： | 板，CD |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | CS5343-DZZR-ND - IC ADC AUD 98DB 108KHZ 10-TSSOP CS5343-CZZR-ND - IC ADC AUD 98DB 108KHZ 10-TSSOP 598-1689-ND - IC ADC AUD 98DB 108KHZ 10TSSOP 598-1189-ND - IC ADC AUD 98DB 108KHZ 10-TSSOP |
| 其它名称： | 598-1156 |
CDB5343
Changing the state of this switch while the device is running will have no effect on the CS5343 as it must
be reset to detect the change. Reset is accomplished by removing and restoring power to the device. Al-
ternatively, removing and restoring MCLK will initiate a reset of the digital section, which is also sufficient
for the CS5343 to detect a change in mode settings.
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
CS8406
This switch sets the CS8406 for either Master Mode or Slave Mode. In Master Mode, the CS5343 must
be configured as a clock slave and “SCLK, LRCK” set to “TO HDR.” In Slave Mode, either the CS5343
can be set to Master Mode or the user can set the “SCLK, LRCK” switch to “FROM HDR.”
MCLK
MCLK can either come from the header, as selected by “FROM HDR,” or from the on-board crystal oscil-
lator (Y1) as selected by “TO HDR.”
SCLK, LRCK
The sub-clocks, SCLK and LRCK, are either produced on board by the CS5343 or the CS8406 or pro-
duced externally. If generated by an external device, this switch must be set to “FROM HDR.” If the
CS5343 or CS8406 generate the sub-clocks, this switch must be set to “FROM HDR.”
SPEED
The CS5343 can operate in Single-Speed Mode (SSM) or Double-Speed Mode (DSM) as described in
the CS5343 product datasheet.
In Master Mode, the CS5343 defaults to SSM based on an internal 100 k Ω pull-up resistor from the LRCK
pin to VA. Setting the “SPEED” switch to “DSM” will place a 10 k Ω pull-down resistor between LRCK and
GND to select Double-Speed Mode. Because the CS5343 determines its Master Mode speed based on
start-up options, the speed mode cannot be toggled during operation. To change the speed in Master
Mode, the device must be reset by removing and restoring power or removing and restoring MCLK.
This switch also configures the MCLK/LRCK ratio for the CS8406. Selecting SSM configures the CS8406
for a 512x MCLK/LRCK ratio while DSM sets an MCLK/LRCK ratio of 256x. In this design, the CS8406
cannot support of a 384x MCLK/LRCK ratio.
MCLK/LRCK Ratio
This switch will configure the CS5343 for either a 256x MCLK/LRCK ratio or a 384x MCLK/LRCK ratio in
Master Mode. In Slave Mode the CS5343 auto-detects the MCLK/LRCK ratio; therefore this configuration
step is unnecessary in Slave Mode. In Master Mode, selection of this parameter is performed via a start-
up option. An internal 100 k Ω pull-up resistor from the SCLK pin to VA will select 256x by default. An ex-
ternal 10 k Ω pull-down resistor from the SCLK pin to GND will select an MCLK/LRCK ratio of 384x.
Typical applications that use a 384x MCLK/LRCK ratio derive a 48 kHz LRCK from a 18.384 MHz MCLK.
Deriving MCLK from the included 12.288 MHz crystal oscillator will result in a sample rate of 32 kHz.
The CS8406 is not configured to support a 384x MCLK/LRCK ratio in this design; therefore analysis in
this mode must be performed by retrieving data through the interface header (J3).
DS687DB2
7
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