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参数资料
| 型号： | CDB5346 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 25/38页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5346 |
| 标准包装： | 1 |
| ADC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | 串行 |
| 输入范围： | 3.15 Vpp |
| 在以下条件下的电源（标准）： | 205mW @ 192kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5346 |
| 已供物品： | 板，缆线，CD |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | CS5346-CQZR-ND - IC ADC AUD 103DB 200KHZ 48-LQFP 598-1692-ND - IC ADC AUD 103DB 200KHZ 48LQFP |
| 其它名称： | 598-1790 |
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DS861PP3
31
CS5346
7.7
Channel A PGA Control - Address 08h
7.7.1
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 10 for ex-
ample settings.
7.8
ADC Input Control - Address 09h
7.8.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 11.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 11.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on asignal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 11.
7
65
432
10
Reserved
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
Gain[5:0]
Setting
101000
-12 dB
000000
0 dB
011000
+12 dB
Table 10. Example Gain and Attenuation Settings
7
65
432
10
Reserved
PGASoft
PGAZero
Sel2
Sel1
Sel0
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