参数资料
型号: CDB5463U
厂商: Cirrus Logic Inc
文件页数: 8/46页
文件大小: 0K
描述: BOARD EVAL & SOFTWARE CS5463 ADC
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS5463
主要属性: 1 相,能量至频率输出
次要属性: GUI、USB、SPI 接口
已供物品:
产品目录页面: 754 (CN2011-ZH PDF)
相关产品: CS5463-ISZR-ND - IC ENERGY METERING 1PHASE 24SSOP
598-1192-5-ND - IC PWR/ENERGY METER 2CH 24-SSOP
598-1096-5-ND - IC ENERGY METERING 1PHASE 24SSOP
其它名称: 598-1553
CS5463
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
Analog Inputs (Voltage Channel)
Differential Input Range
Total Harmonic Distortion
[(VIN+) - (VIN-)]
VIN
THD
-
65
500
75
-
-
mV P-P
dB
Crosstalk with Current Channel at Full Scale (50, 60 Hz)
-
-70
-
dB
Input Capacitance All Gain Ranges
Effective Input Impedance
Noise (Referred to Input)
Offset Drift (Without the High Pass Filter)
IC
EII
N V
OD
-
2
-
-
0.2
-
140
16.0
-
-
-
-
pF
M ?
μV rms
μV/°C
Gain Error
(Note 3)
GE
-
±3.0
%
Temperature Channel
Temperature Accuracy
T
-
±5
-
°C
Power Supplies
Power Supply Currents (Active State) I A+
I D+ (VA+ = VD+ = 5 V)
I D+ (VA+ = 5 V, VD+ = 3.3 V)
Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 4) Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-by State
Sleep State
PSCA
PSCD
PSCD
PC
-
-
-
-
-
-
-
1.1
2.9
1.7
21
11.6
8
10
-
-
-
29
17.5
-
-
mA
mA
mA
mW
mW
mW
μW
Power Supply Rejection Ratio (50, 60 Hz)
-
-
(Note 5) Voltage Channel
Current Channel
PFMON Low-voltage Trigger Threshold (Note 6)
PFMON High-voltage Power-on Trip Point (Note 7)
PSRR
PMLO
PMHI
45
70
2.3
-
65
75
2.45
2.55
-
-
-
2.7
dB
dB
V
V
PSRR = 20 ? log ----------
Notes: 3. Applies before system calibration.
4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV
(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The
“+” and “-” input pins of both input channels are shorted to AGND. Then the CS5463 is commanded to
continuous conversion acquisition mode, and digital output data is collected for the channel under test.
The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted
into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined
as Veq. PSRR is then (in dB) :
150
V eq
6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
8
DS678F3
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