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| 型号： | CDCLVP2104RHDR |
| 厂商： | Texas Instruments |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER 2:8 2GHZ 28-VQFN |
| 标准包装： | 3,000 |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 2 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | LVPECL |
| 频率 - 最大： | 2GHz |
| 电源电压： | 2.375 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-VQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
SCAS889A
– OCTOBER 2009 – REVISED AUGUST 2011
ELECTRICAL CHARACTERISTICS: LVPECL Output
(1)
At VCC = 2.375 V to 2.625 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP2104
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Output high voltage
VCC – 1.26
VCC – 0.9
V
VOL
Output low voltage
VCC – 1.7
VCC – 1.3
V
VOUT, DIFF, PP
Differential output peak-peak voltage
fIN ≤ 2 GHz
0.5
1.35
V
VAC_REF
Input bias voltage(2)
IAC_REF = 2 mA
VCC – 1.6
VCC – 1.1
V
VIN, DIFF, PP = 0.1V
450
ps
tPD
Propagation delay
VIN, DIFF, PP = 0.3V
450
ps
tSK,PP
Part-to-part skew
125
ps
tSK,O_WB
Within bank output skew
15
ps
tSK,O_BB
Bank-to-bank output skew
Both inputs have equal skew
20
ps
Crossing-point-to-crossing-point
tSK,P
Pulse skew (with 50% duty cycle input)
–50
50
ps
distortion, fOUT = 100 MHz
fOUT = 100 MHz, VIN,SE = VCC,
0.089
ps, RMS
Vth = 1.25 V, 10 kHz to 20 MHz
fOUT = 100 MHz, VIN,SE = 0.9 V,
0.093
ps, RMS
Vth = 1.1 V, 10 kHz to 20 MHz
Random additive jitter (with 50% duty
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
tRJIT
0.037
ps, RMS
cycle input)
VICM = 1 V, 10 kHz to 20 MHz
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
0.094
ps, RMS
VICM = 1 V, 10 kHz to 20 MHz
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
0.091
ps, RMS
VICM = 1 V, 10 kHz to 20 MHz
fOUT,4 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V,
VICM, 0 = 1 V, fOUT, 3 = 62.5 MHz,
–50.1
dBc
VIN,SE,1 = VCC, Vth, 1 = VCC/2
fOUT,4 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V,
VICM, 0 = 1 V, fOUT, 3 = 62.5 MHz,
–64.3
dBc
Coupling on differential OUT4 from
VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V
OUT3 in the frequency spectrum
PSPUR
of fOUT, 4 ±(fOUT, 4/2) with
fOUT,4 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V,
synchronous inputs
VICM, 0 = 1 V, fOUT, 3 = 15.625 MHz,
–49.8
dBc
VIN,SE,1 = VCC, Vth, 1 = VCC/2
fOUT,4 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V,
VICM, 0 = 1 V, fOUT, 3 = 15.625 MHz,
–64.3
dBc
VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V
tR/tF
Output rise/fall time
20% to 80%
200
ps
IEE
Supply internal current
Outputs unterminated
78
mA
ICC
Output and internal supply current
All outputs terminated, 50
to VCC – 2
330
mA
(1)
(2)
Internally generated bias voltage (VAC_REF) is for 3.3-V operation only. It is recommended to apply externally generated bias voltage for
VCC < 3.0 V.
4
Copyright
2009–2011, Texas Instruments Incorporated
Product Folder Link(s): CDCLVP2104
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