参数资料
型号: CGS3322MX
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 时钟产生/分配
中文描述: 110 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, MS-012, SOIC-8
文件页数: 2/6页
文件大小: 151K
代理商: CGS3322MX
www.fairchildsemi.com
2
C
G
S3321
C
G
S3322
Pin Descriptions
Note: Pin out varies for each device.
Block Diagrams
Note: Pin numbers vary for each device
Note: Pin out varies for each device.
OSC_IN
Input to Oscillator Inverter. The output of the
crystal would be connected here.
OEH
Active HIGH 3-STATE enable pin. This pin pulls
to a HIGH value when left floating and 3-
STATEs the output when forced LOW. This pin
has TTL compatible input levels.
OSC_OUT Resistive Buffered Output of the Oscillator
Inverter
OUT
This pin is the main clock output on the device.
DIVB
(CGS3322 only)
3-Level input used to select Binary Divide-by
value of output frequency.
OSCLO_1
The Oscillator LOW pin is the ground for the
Oscillator.
DC_ADJ
(CGS3321 only)
Active high input that controls output duty
cycle. Logic high level will delay the HL transi-
tion edge approximately 0.3 ns.
VCC
The power pin for the chip.
GND
The ground pin for all sections of the circuitry
except the oscillator and oscillator related
circuitry.
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