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参数资料
| 型号： | CIC-FILT-E2-UT2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 21/33页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE CIC FILTER EC/ECP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | CICFILTE2UT2 |
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Chapter 4:
IP Core Generation
This chapter provides information on how to generate the CIC Filter IP core using the Diamond or ispLEVER soft-
ware IPexpress tool, and how to include the core in a top-level design.
Licensing the IP Core
An IP core- and device-specific license is required to enable full, unrestricted use of the CIC Filter IP core in a com-
plete, top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at:
Users may download and generate the CIC Filter IP core and fully evaluate the core through functional simulation
and implementation (synthesis, map, place and route) without an IP license. The CIC Filter IP core also supports
Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in
hardware for a limited time (approximately four hours) without requiring an IP license. See “Hardware Evaluation”
on page 26 for further details. However, a license is required to enable timing simulation, to open the design in the
Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evaluation timeout
limitation.
Getting Started
The CIC Filter IP core is available for download from the Lattice IP Server using the IPexpress tool. The IP files are
automatically installed using ispUPDATE technology in any customer-specified directory. After the IP core has
The IPexpress tool GUI dialog box for the CIC Filter IP core is shown in Figure 4-1. To generate a specific IP core
configuration the user specifies:
? Project Path – Path to the directory where the generated IP files will be loaded.
? File Name – “username” designation given to the generated IP core and corresponding folders and files.
? (Diamond) Module Output – Verilog or VHDL.
? (ispLEVER) Design Entry Type – Verilog HDL or VHDL.
? Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3,
etc.). Only families that support the particular IP core are listed.
? Part Name – Specific targeted part within the selected device family.
IPUG42_02.6, August 2010
21
Cascaded Integrator-Comb (CIC) Filter User’s Guide
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|---|---|
| CIC-FILT-E3-U2 | 功能描述:开发软件 CASCADED INTEGRATOR COMB FILTER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CIC-FILT-E3-UT2 | 功能描述:开发软件 CASCADE INTEGRATOR COMB FILTER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CIC-FILT-P2-U2 | 功能描述:开发软件 Cascaded Integrator Comb Filter RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CIC-FILT-P2-UT2 | 制造商:Lattice Semiconductor Corporation 功能描述: |
| CIC-FILT-PM-U2 | 功能描述:开发软件 Cascaded Integrator Comb Filter RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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