参数资料
| 型号： | COP8CDR9IMT8 |
| 厂商： | National Semiconductor |
| 文件页数： | 92/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 48-TSSOP |
| 标准包装： | 38 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 39 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 包装： | 管件 |
| 其它名称： | *COP8CDR9IMT8 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页当前第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
should return to execute the VIS instruction. This is particularly useful when exiting long interrupt
service routines if the time between interrupts is short. In this case the RETI instruction would only be
executed when the default VIS routine is reached.
3. While executing from the Boot ROM for ISP or virtual E2 operations, the hardware will disable
interrupts from occurring. The hardware will leave the GIE bit in its current state, and if set, the
hardware interrupts will occur when execution is returned to Flash Memory. Subsequent interrupts,
during ISP operation, from the same interrupt source will be lost.
5.16 WATCHDOG/Clock Monitor
The devices contain a user selectable WATCHDOG and clock monitor. The following section is applicable
only if the WATCHDOG feature has been selected in the Option register. The WATCHDOG is designed to
detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway”
programs.
The WATCHDOG logic contains two separate service windows. While the user programmable upper
window selects the WATCHDOG service time, the lower window provides protection against an infinite
program loop that contains the WATCHDOG service instruction. The WATCHDOG uses the Idle Timer
(T0) and thus all times are measured in Idle Timer Clocks.
The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on
tC.
The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER
establishes the upper limit on the service window and WD LOWER defines the lower limit of the service
window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named
WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-
bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 5-26 shows the
WDSVR register.
Table 5-26. WATCHDOG Service Register (WDSVR)
Window Select
Key Data
Clock Monitor
X
0
1
0
Y
7
6
5
4
3
2
1
0
The lower limit of the service window is fixed at 2048 Idle Timer Clocks. Bits 7 and 6 of the WDSVR
register allow the user to pick an upper limit of the service window.
Table 5-27 shows the four possible combinations of lower and upper limits for the WATCHDOG service
window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the
user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at
01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit.
Table 5-27. WATCHDOG Service Window Select
Clock
Service Window
WDSVR
Monitor
for High Speed Mode
for Dual Clock & Low Speed Modes
Bit 7
Bit 6
Bit 0
(Lower-Upper Limits)
0
X
2048-8k tC Cycles
2048-8k Cycles of 32 kHz Clk
0
1
X
2048-16k tC Cycles
2048-16k Cycles of LS 32 kHz Clk
1
0
X
2048-32k tC Cycles
2048-32k Cycles of LS 32 kHz Clk
1
X
2048-64k tC Cycles
2048-64k Cycles of LS 32 kHz Clk
X
0
Clock Monitor Disabled
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
81
相关PDF资料 |
PDF描述 |
|---|---|
| COP8CCR9LVA8 | IC MCU EEPROM 8BIT 68-PLCC |
| C8051F581-IQ | IC 8051 MCU 128K FLASH 48-QFP |
| C8051F584-IQ | IC 8051 MCU 96K FLASH 48-QFP |
| EFM32TG210F32 | MCU 32BIT 32KB FLASH 32-QFN |
| MPC565CZP56 | IC MPU 32BIT IM FLASH 388-PBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COP8CDR9IMTA8 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
| COP8CDR9KMT7 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
| COP8CDR9KMT8 | 功能描述:IC MCU EEPROM 8BIT 32K 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:COP8™ 8C 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| COP8CDR9KMTA8 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
| COP8CDR9LVA7 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
发布紧急采购，3分钟左右您将得到回复。