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| 型号： | CPC5002GSTR |
| 厂商： | IXYS Integrated Circuits Division |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | ISOLAT DGTL 3.75KVRMS 2CH 8-SMT |
| 标准包装： | 1 |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 隔离： | 3750Vrms |
| 数据速率： | 10Mbps |
| 传输延迟： | 81ns |
| 输出类型： | 开路漏极 |
| 封装/外壳： | 8-SMD，鸥翼型 |
| 供应商设备封装： | 8-SMD |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | CLA384DKR |
I NTEGRATED C IRCUITS D IVISION
CPC5002
4.2 Application Example
Shown below is an example of an isolated POE Controller SMBus where the SDA signal has been split into separate
SDA IN and SD OUT signals on the isolated slave side of the barrier. In this example, the low power SMBus master, not
shown, requires a buffer (U3) capable of driving the CPC5002 input LEDs. Although selection of the appropriate
buffer is determined by the product definition and the ability to drive the LED’s, it is recommended the buffer have
Schmitt trigger inputs to ensure clean bounce-free LED drive signals. A high power SMBus master with the ability to
sink 4mA of pullup current may not require a buffer to drive the CPC5002 inputs. In this example, the POE Controllers
are specified as SMBus high power and I 2 C compatible. This enables the POE Controllers to drive the CPC5002
LEDs directly without the need of an external buffer.
Circuit design of the SMBus physical layer using the CPC5002 consists of two parts, one being the LED input drive
current and the other being the buffered galvanically isolated logic output signals.
The following design constraints are assumed for this example:
?
?
?
Supply Voltages: V DDx = 3.0V to 3.6V
Ambient Temperature: T A = 0°C to 70°C
V OL ? 0.4V for U3 and the POE Controllers
? I OL ? 4mA for U3 and the POE Controllers
? Resistors:
? Tolerance = 1%
? Temperature Coefficient = 100ppm
Figure 3. Optically isolated SMBus for POE Controllers with Separate SDA IN and SDA OUT Pins
3.3 V DDM
1
U1
CPC5002
3.3 V DDS
8
SCL M
SDA M
U3
R1
8 06 Ω 2
R2
8 06 Ω 3
3.3 V DDM
4
7
6
5
3.3 V DDS
R5
511 Ω
3.3 V DDS
R6
511 Ω
3.3 V DDS
0.1 μ F
SMB u s
POE
Controllers
SCL
SDA I N
I N T
SDA OUT
0.1 μ F
G N D M
G N D S
3.3 V DDM
8
U2
CPC5002
1
3.3 V DDS
2 8 06 Ω
INT M
3.3 V DDM
R7
10k
3.3 V DDM
R 8
10k
7
6
3.3 V DDS
R3
R9*
3.3 V DDS
R4
R10*
3 8 06 Ω
SCL
SDA I N
I N T
SDA OUT
3.3 V DDM
3.3 V DDS
* R9 and R10 are not re qu ired for this design.
See text for explanation.
0.1 μ F
G N D M
5
4
0.1 μ F
G N D S
To minimize pulse width distortion of the output signal, the input LED drive current needs to be set at the lower end of
it’s operational range. Because the forward voltage of the LED has a negative temperature coefficient this will occur at
the minimum operating temperature point with the minimum supply voltage. With V DD = 3.0V and V F = 1.442V at
T A = 0°C and I F = 1.4mA, the calculated maximum value for the series input resistor R S is 826.8 ? . Taking tolerance
and value change due to temperature into account, the nearest E96 standard value sets R S = 806 ? . Using
V OL_Nominal = 0.25V and V OL_Minimum = 0.1V and calculating for the LED current range over the specified operating
conditions with R S = 806 ? , the LED input current I F will be 1.455mA to 3.212mA. At nominal operating conditions with
T A = 25°C, the nominal LED input current is: I F_Nominal = 2.28mA.
10
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