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参数资料
| 型号： | CPC5002GSTR |
| 厂商： | IXYS Integrated Circuits Division |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | ISOLAT DGTL 3.75KVRMS 2CH 8-SMT |
| 标准包装： | 1 |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 隔离： | 3750Vrms |
| 数据速率： | 10Mbps |
| 传输延迟： | 81ns |
| 输出类型： | 开路漏极 |
| 封装/外壳： | 8-SMD，鸥翼型 |
| 供应商设备封装： | 8-SMD |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | CLA384DKR |
I NTEGRATED C IRCUITS D IVISION
CPC5002
For the outputs, the CPC5002 is compatible with both SMBus and Fast-mode I 2 C compatible devices. As with all
mixed type devices on a bus, the weakest driver on that bus determines the minimum value of the pullup resistor.
When the CPC5002 is the only device driving the bus as shown with U1, the minimum E96 standard value for pullup
resistors R5 and R6 will be 511 ? . For bus loading up to 400pF, this pullup resistor value will provide for Fast-mode
compliant I 2 C bus speeds. At lower data rates or with less capacitive bus loading, the actual resistor value selected
can be higher.
When the CPC5002 shares a bus with another device as is the case with U2, the weakest driver sets the conditions
for selecting the correct resistor value. As stated earlier, the SMBus master is rated as a Low-power device and
therefore is only capable of sinking 350uA to an output low voltage level of 0.4V. A pullup resistor attached to the
maximum supply voltage level of 3.6V and pulled down by this low power driver limits the minimum pullup resistor
value to 9.14k ? . After considering tolerance and temperature effects the nearest E96 standard value is 9.31k ? . Most
applications will typically select the more common 10k ? value for R7 and R8, which allows for a 5% resistor tolerance.
Although shown but not needed in this example are pullup resistors R9 and R10. These resistors, not needed by the
CPC5002 at U2, are utilized whenever the busses they are attached to are also connected to device(s) having logic
level inputs. With heavy loading or excessive leakage on the bus the resistors provide supplementary bias to improve
pullup transition performance and to increase the output logic high level without impacting the LED input current bias
level.
The CPC5002 can be utilized to provide digital isolated buffering in a variety of unique applications. Design support is
available by contacting IXYS Integrated Circuits Division’s Applications.
R03
www.ixysic.com
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