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| 型号： | CPC5002GSTR |
| 厂商： | IXYS Integrated Circuits Division |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | ISOLAT DGTL 3.75KVRMS 2CH 8-SMT |
| 标准包装： | 1 |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 隔离： | 3750Vrms |
| 数据速率： | 10Mbps |
| 传输延迟： | 81ns |
| 输出类型： | 开路漏极 |
| 封装/外壳： | 8-SMD，鸥翼型 |
| 供应商设备封装： | 8-SMD |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | CLA384DKR |
I NTEGRATED C IRCUITS D IVISION
3 Functional Description
3.1 Introduction
The CPC5002 provides two independent galvanically
isolated high speed open-drain output optical isolators
in a single 8-pin package. It exhibits excellent isolation
(3750V rms ) and speed (10Mbps typical), and operates
over a wide range of supply voltages (2.7V to 5.5V).
Because the active circuits have been fabricated in a
CMOS process, the device requires much less supply
current (1.4mA typical with V DD = 3.3V) and can run at
much lower LED currents (1.4mA minimum) than
similar devices fabricated with bipolar processes.
3.2 Functional Description
An open-drain output of the CPC5002 will activate and
sink current when the light generated by the LED and
passed across the barrier to the photodetector is
sufficient. The minimum level of input current
necessary to initiate this behavior is referred to as the
LED Input Threshold Current (I TH ) and is a function of
the optical current transfer ratio of the device.
To provide consistent performance over the LED Input
Threshold Current range, the recommended typical
LED drive current (I F ) over temperature and all
operating conditions, is 1.5mA. This recommendation
is provided to offer a balance in the propagation
delays on both the falling and rising edges of the
signal pulse being buffered across the barrier. The
absolute value of the mismatch in the delay of these
two edges is Pulse Width Distortion. In the
specifications these delays are identified as t PHL and
t PLH while the distortion is PWD.
In general, choosing a higher LED drive current will
decrease t PHL , the propagation time for the output to
go from high to low. This is mostly due to the LED
generating more light more quickly as it turns on.
However, if I F is more than 2 x I TH then increasing the
LED drive current further will cause t PLH , the
propagation time for the output to go from low to high,
to increase.
Excess levels of I F makes the difference between t PLH
and t PHL (also known as pulse width distortion)
greater. Pulse width distortion is often of interest when
the signal being isolated is a clock. Keeping the LED
CPC5002
drive current near 1.5mA and using the minimum R PU
and C L at the output reduces the worst case pulse
width distortion and is thus recommended for best
waveform fidelity.
When using 1.5mA of LED drive current and when the
CPC5002 is driving a fast output bus (one with
minimum R PU and C L ), the average t PHL will usually
be slightly longer than the average t PLH . In this case,
reduction of average pulse width distortion can be
accomplished by using a small feed forward capacitor.
The capacitor boosts the instantaneous current
applied to the LED at turn-on (reducing t PHL ) while
leaving the applied DC input current at 1.5mA (t PLH
unchanged). Examples of the feed forward capacitor
(C FWD ) are shown in "Figure 1. Inverting
Configuration” on page 9 and "Figure 2.
Non-Inverting Configuration” on page 9 .
Increasing the value of the feed forward capacitor
causes t PHL to decrease. For a 499 ? pullup into a
20pF load capacitance (C L ), a 10pF capacitor across
the series resistor will minimize pulse width distortion
of an average unit.
When parallel digital signals are to be isolated,
propagation delay skew (t PSK ) becomes important. It
is defined as the absolute value of the difference
between the maximum and minimum propagation
delays (i.e. the worse of ?? t PLH or ? t PHL ) for any group
of optical isolator channels operating under the same
conditions. For the CPC5002, the delay t PLH has a
wider variation with differing optical current transfer
ratios than the delay t PHL . Additionally, t PLH will exhibit
variation due to R PU and C L differences between
channels. If one channel is to be used as a clock and
another for data, it is recommended to use the
CPC5002 output falling edge to latch the data as this
edge will exhibit less channel-to-channel or
part-to-part timing variation and thus will reduce worst
case timing skew.
In general the current transfer ratio matching between
the two channels in a single CPC5002 is better than
the ratio matching between multiple parts. Thus the
channel to channel skew for two signals isolated
through the same CPC5002 will be statistically better
than skew measured between signals isolated through
multiple parts.
8
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