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| 型号： | CPC5902G |
| 厂商： | IXYS Integrated Circuits Division |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | ISOLAT 3.75KVRMS 2CH BIDIR 8DIP |
| 标准包装： | 50 |
| 电压 - 隔离： | 3750Vrms |
| 通道数： | 2，双向 |
| 数据速率： | 400kbps |
| 输入类型： | AC，DC |
| 输出类型： | I²C? |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-DIP |
| 包装： | 管件 |
| 其它名称： | CLA380 |
I NTEGRATED C IRCUITS D IVISION
3 Functional Description
3.1 Overview
The CPC5902 combines the features of multiple logic
optoisolators and an I 2 C bus repeater in a single 8-pin
package. It offers excellent isolation (3750V rms ) and
speed sufficient to support I 2 C Fast-mode at 400kbps.
It bidirectionally buffers the two I 2 C signals across the
isolation barrier, and supports I 2 C clock stretching. If
different supply voltage levels are used at each side,
then the part, in conjunction with its external pullup
resistors, will perform logic level translation for V DD
between 2.7V and 5.5V at either side.
The CPC5902, like available non-galvanically isolating
I 2 C bus repeaters, has a full drive side and a limited
drive side. It uses a voltage-limited output driver and a
lower V THRESHOLD (V IL ) at the Side B IO. The
voltage-limited Side B output driver can not output a
V OL level below an internally set voltage limit. This is
necessary to ensure that the CPC5902 cannot drive
its own IOB input to a level it accepts as a logic low,
which would cause I 2 C bus contention. The parts are
specified with a minimum V OL -V IL margin of 25mV at
minimum V DDB , and exhibit a proportionately larger
self-drive margin with larger V DDB .
The Side A drivers are Fast-mode, full strength (6mA)
over the full V DDA range, and the input thresholds are
specified to be Fast-mode compliant; thus Side A will
drive up to the full 400pF Fast-mode C LOAD and is
allowed to drive its own input to a logic low. Devices
meeting the I 2 C specification are easily able to drive
the IO nodes below the CPC5902’s lower V IL
(0.2V DDB ) threshold at the Side B inputs, and will
correctly accept the CPC5902 Side B driven data,
thereby enabling Side B bidirectional communication
at up to 3mA of load current over the full V DDB range.
Over the entire V DDx range, Side A is fully I 2 C
Fast-mode compliant while Side B is I 2 C
Standard-mode compliant. It is important to note that
Side B can be operated at the Fast-mode date rate
when the capacitive loading on the bus is kept at
200pF or less, however when V DDB > 4.5V, Side B is
also Fast-mode compliant with up to 400pF capacitive
loading.
CPC5902
IO pullup resistors are required on both sides of the
barrier. At the Side B inputs, resistor values should be
chosen for Standard-mode 3mA pullup current (for
operation independent of V DDB ). Pullups chosen for
Fast-mode drivers (up to 6mA) can be used at Side A
with no loss of noise margin.
Applying a pulse at a Side B input inherently involves
the use of some of the output driver circuits at that I/O.
In a manner similar to the I 2 C clock stretching feature,
once an asserted signal is determined to be valid, it is
stretched until its proper transmission through the
optics has been verified. This insures that there will be
no extra edges generated at either side due to optic
delays. If a Side B asserted-low pulse is long enough
to be accepted and passed to Side A, then the flip-flop
at Side B is set and remains set until the signal returns
through the optics from Side A.
In operation, a valid asserted pulse of less than 80ns
applied at Side B appears at Side A after a delay
largely determined by the low-pass filter delay (t FIL )
and the optics delay (t OPHL_BA ). After this initial delay
the Side A driver is activated and a logic low is
asserted at time:
t STARTA = t FIL + t OPHL_BA
That assertion is returned across the optics to Side B
after a delay largely determined by t OPHL_AB . Upon
arriving at Side B, the flip-flop is cleared, and the
deassertion is sent through the optics to Side A,
arriving at the Side A output after a delay largely
determined by t OPLH_BA at time:
t ENDA = t FIL + t OPHL_BA + t OPHL_AB + t OPLH_BA
Thus a valid Side B pulse having a width less than
80ns is stretched at Side A to a typical width of 125ns.
The duration of the pulse width output onto the Side A
bus is given by:
t PWA_min = (t OPHL_AB + t OPLH_BA )
When Side A is deasserted, the output rises at a slew
rate determined by the RC load on IOA, and passes
the logic threshold after time t SLEWA . The deasserted
(logic HIGH) input propagates through the optics and
deasserts the Side B output after a delay largely
8
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| CPC5902G_5903G-EVAL | 功能描述:CPC5902, CPC5903 - Interface, Buffer/Repeater Evaluation Board 制造商:ixys integrated circuits division 系列:- 零件状态:有效 主要用途:接口，缓冲器/中继器 嵌入式:- 使用的 IC/零件:CPC5902，CPC5903 主要属性:隔离 辅助属性:- 所含物品:板 标准包装:1 |
| CPC5902GS | 功能描述:ISOLAT 3.75KVRMS 2CH BIDIR 8SMD RoHS:是 类别:隔离器 >> 光隔离器 - 逻辑输出 系列:- 标准包装:1,000 系列:- 电压 - 隔离:3750Vrms 通道数:1，单向 电流 - 输出 / 通道:50mA 数据速率:15MBd 传输延迟高 - 低 @ 如果:50ns @ 7.5mA 电流 - DC 正向(If):20mA 输入类型:DC 输出类型:开路集电极 安装类型:表面贴装 封装/外壳:8-SMD，鸥翼型 供应商设备封装:8-DIP 鸥翼型 包装:带卷 (TR) |
| CPC5902GSTR | 功能描述:ISOL 3.75KVRMS 2CH BIDIR 8-SMD RoHS:是 类别:隔离器 >> 光隔离器 - 逻辑输出 系列:- 标准包装:50 系列:- 电压 - 隔离:3750Vrms 通道数:1，单向 电流 - 输出 / 通道:10mA 数据速率:25MBd 传输延迟高 - 低 @ 如果:20ns 电流 - DC 正向(If):- 输入类型:逻辑 输出类型:推挽式/图腾柱 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:516-1112-5 |
| CPC5903G | 功能描述:ISOL 3.75KVRMS 1CH BIDIR 8-DIP RoHS:是 类别:隔离器 >> 光隔离器 - 逻辑输出 系列:- 标准包装:50 系列:- 电压 - 隔离:3750Vrms 通道数:1，单向 电流 - 输出 / 通道:10mA 数据速率:25MBd 传输延迟高 - 低 @ 如果:20ns 电流 - DC 正向(If):- 输入类型:逻辑 输出类型:推挽式/图腾柱 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:516-1112-5 |
| CPC5903GS | 功能描述:ISOL 3.75KVRMS 1CH BIDIR 8-SMD RoHS:是 类别:隔离器 >> 光隔离器 - 逻辑输出 系列:- 标准包装:50 系列:- 电压 - 隔离:3750Vrms 通道数:1，单向 电流 - 输出 / 通道:10mA 数据速率:25MBd 传输延迟高 - 低 @ 如果:20ns 电流 - DC 正向(If):- 输入类型:逻辑 输出类型:推挽式/图腾柱 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:516-1112-5 |
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