参数资料
型号: CPD250-4530G
厂商: Power-One
文件页数: 10/19页
文件大小: 0K
描述: PWR SUP 250W 3.3/5/12/-12V QUAD
标准包装: 20
系列: CPD
类型: 隔离
输入电压: 36 ~ 75V
输出: 5V,3.3V,±12V
输出数: 4
输出 - 1 @ 电流(最大): 5 VDC @ 40A
输出 - 2 @ 电流(最大): 3.3 VDC @ 40A
输出 - 3 @ 电流(最大): 12 VDC @ 5.5A
输出 - 4 @ 电流(最大): -12 VDC @ 2A
功率(瓦特): 250W
安装类型: Compact PCI®
效率: 82.2%
封装/外壳: 模块
尺寸/尺寸: 6.40" L x 1.60" W x 5.07" H(162.5mm x 40.6mm x 128.7mm)
包装: 散装
电源(瓦特)- 最大: 250W
批准: CE,CSA,cUL,EN,TUV,UL
产品目录页面: 2739 (CN2011-ZH PDF)
其它名称: 179-2281
CPD250-4530-G

CPA, CPD Series Data Sheet
?
200 – 550 Watt
CompactPCI ?
AC-DC and DC-DC Converters
P o / P o nom
1.0
JM012b
300 LFM = 1.5 m/s (CPA/CPD500)
400 LFM = 2 m/s (CPA550)
drops back below this limit; see Temperature Warning and
Shutdown.
Output Filter
Convection cooling
in upright position
The output ripple voltage can be reduced by an external filter to
less then 5 mV pp . Recommended values:
0.6
0.5
CPA550
CPA/CPD500
? C1, C2: Low ESR capacitor, e.g., OS-CON 100 – 470 μF
? L1, L2: Choke 1 – 4.7 μH with appropriate rated current,
e.g., Coiltronics ? HC2LP 1 μH /33 A or 2.2 μH /24 A.
JM010
0
Fig. 4c
T A min
40
50
60
70
80
90 °C
46
30
1–4
Vo1SENSE
Vo1
L 1
5V
L 2
Output powerversus T A at V inom (CPA500/550,CPD500)
Note : Forced-air cooling (or an additional heat sink on
customer-specific models) can improve the reliability or allow
for higher T A , as shown in the diagrams fig. 4, but T C max shall
never be exceeded.
A temperature sensor fitted on the main PCB provides approx.
47
33
13 –18
5 –12
Vo2SENSE
Vo2
RTN
C 2
+
+
C 1
3.3 V
Gnd
20 °C below T C max a warning signal (DEG#), at which the
control logic begins to reduce the output power. The output
power returns to the normal value, when the temperature
Auxiliary Functions
Inhibit and Enable
The inhibit input INH# enables (logic high) or disables (logic
low, pull down) all outputs, when a logic signal (TTL, CMOS) is
applied. In systems consisting of several converters this
feature may be used to control the activation sequence of the
converters or to enable the source to start-up, before full load
06153d
Fig. 5
Output filter reducing the output ripple of Vo1 and Vo2
is applied. When INH# is low, the converter cannot be
activated by the EN# pin
Note: If this function is not used, the inhibit pin 39 can be left
open-circuit (not connected). If pin 39 is connected to a return
pin (e.g. pin 22), the internal logic will disable all outputs. The
inhibit input is protected by a decoupling diode.
EN# (pin 27) is CMOS-compatible. However, we recommend
to connect it directly with a return pin (e.g. pin 22) to enable the
converter. Pin 27 is shorter than the others, ensuring start-up
only, after all other pins were connected to the system. This
provides true hot-swap capability.
Note : When a CPA or CPD500 converter is disabled by INH# and/
46
INH#
39
or EN #, the PFC booster remains active, keeping the boost
capacitor C b (fig. 1) charged. As a result, there is no inrush
current at restart.
EN#
27
V INH#
Note : When a CPD 500/550 converter is disabled, on outputs 3
and 4 may appear a little voltage under no-load condition. This
can be avoided by a small preload.
47
RTN
(22)
V o / V o nom
06155a
Fig. 6
1
Inhibit and enable inputs
Table 6: Inhibit data
0.1
0
t r
t f
t
Characteristics
Conditions
min
typ max Unit
Inhibit
V inh
Inhibit
V o = off V i min – V i max
– 2
0.8
V
1
t r
voltage
Rise time
V o = on
I o = 0 – I o max
2.4
50
120
ms
Fig. 7
0
t
t f
Fall time
depending on I o
Typical output response as function of inhibit voltage.
BCD20005-G Rev. AG2, 20-Dec-2012
Page 10 of 19
www.power-one.com
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