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| 型号： | CRD5463PM |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 37/46页 |
| 文件大小： | 0K |
| 描述： | REFERENCE DESIGN FOR POWER METER |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5463 |
| 主要属性： | 单相功率表 |
| 次要属性： | 90 ~ 260 VAC |
| 已供物品： | 模块，适配器，线缆，电源线 |
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CS5463
7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5463 provides digital DC offset and gain com-
pensation that can be applied to the instantaneous volt-
age and current measurements, and AC offset
compensation to the voltage and current RMS calcula-
tions.
Since the voltage and current channels have indepen-
dent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one channel affecting the oth-
er.
The computational flow of the calibration sequences are
illustrated in Figure 12. The flow applies to both the volt-
N + 30 conversion cycles to complete. For AC offset cal-
ibrations, the sequence takes at least 6N + 30 ADC cy-
cles to complete, (about 6 computation cycles). As N is
increased, the accuracy of calibration results will in-
crease.
7.1.2 Offset Calibration Sequence
For DC and AC offset calibrations, the VIN ? pins of the
voltage and IIN ? pins of the current channels should be
connected to their ground reference level. (see Figure
13.)
External
Connections
age channel and current channel.
7.1.1 Calibration Sequence
0V +-
AIN+
+
XGAIN
+
The CS5463 must be operating in its active state and
ready to accept valid commands. Refer to Section 5.16
CM +-
AIN-
-
-
Commands on page 23. The calibration algorithms are
dependent on the value N in the Cycle Count Register
(see Figure 12). Upon completion, the results of the cal-
ibration are available in their corresponding register.
The DRDY bit in the Status Register will be set. If the
DRDY bit is to be output on the INT pin, then DRDY bit
in the Mask Register must be set. The initial values in
the AC gain and offset registers do affect the results of
the calibration results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5463
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
Figure 13. System Calibration of Offset
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the av-
erage of the instantaneous samples collected over a
computational cycle. Upon completion of the DC offset
calibration the DC offset is stored in the corresponding
DC offset register. The DC offset value will be added to
to V*, I* Registers
?
In
Modulator
Filter
+
+
+
X
X
N
? N
?
+
+
+
V RMS *, I RMS *
Registers
?
DC Offset*
Gain*
N
AC Offset*
-1
X
Inverse
? N
-1
X
0.6
RMS
* Denotes readable/writable register
Figure 12. Calibration Data Flow
DS678F3
37
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| CRD5463PM-Z | 功能描述:REFERENCE DESIGN FOR POWER METER RoHS:否 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| CRD5490-Z | 功能描述:电源管理IC开发工具 CS5463 Pwr Meas/Mntr Reference Design RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| CRD5AS-12B | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Reverse Conducting Thyristor Medium Power Use |
| CRD5AS-12B#B00 | 功能描述:SCR 600V 7.8A Sensitive Gate Surface Mount MP-3A 制造商:renesas electronics america 系列:- 包装:管件 零件状态:有效 电压 - 断态:600V 电压 - 栅极触发（Vgt）（最大值）:800mV 电流 - 栅极触发（Igt）（最大值）:100μA 电压 - 通态（Vtm）（最大值）:1.8V 电流 - 通态（It（AV））（最大值）:5A 电流 - 通态（It（RMS））（最大值）:7.8A 电流 - 保持（Ih）（最大值）:3mA 电流 - 断态（最大值）:2mA 电流 - 不重复浪涌 50，60Hz（Itsm）:90A @ 60Hz SCR 类型:灵敏栅极 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:TO-252-3，DPak（2 引线+接片），SC-63 供应商器件封装:MP-3A 标准包装:1 |
| CRD5AS-12BB00 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Reverse Conducting Thyristor Medium Power Use |
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