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| 型号： | CS1501-FSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC PFC CONTROLLER DCM OCP 8SOIC |
| 产品变化通告： | CS1501, 1601 Datasheet Update Change 11/Jan/2012 |
| 设计资源： | CS150x/160x PCB Layout Guidelines Driving Mosfets with CS1501/1601 CS1501/1601 Driving ZCD Pin from Mosfet Drain |
| 特色产品： | CS1501/CS1601 Power Factor Correction IC Controllers |
| 标准包装： | 100 |
| 模式： | 临界传导（CRM），间歇导电（DCM） |
| 频率 - 开关： | 70kHz |
| 电流 - 启动： | 68µA |
| 电源电压： | 7.9 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 散装 |
| 其它名称： | 598-1912 |
CS1501
5.3 Burst Mode
Burst mode is used to improve system efficiency when the
Solving Equation 2 for the PFC boost inductor, L B , gives the
following equation:
L B = ? ? ? ? ? 90V ? ? -------------------------------------------------------------
system output power (P o ) is <5% of nominal. Burst mode is
implemented by intermittently disabling the PFC over a full
half-line period under light-load conditions, as shown in
2 400V – ? 90V ? 2 ?
2 ? 70kHz ? P o ? 400V
[Eq.3]
If a value of the boost inductor other than that obtained from
P o
[W]
Burst Threshold
Burst Mode
Equation 3 above is used, the total output power capability
and the minimum input voltage threshold will differ according
to Equation 2. Note that if the input voltage drops below
90Vrms and the inductance value is <L B , the link voltage V link
will drop below 400V and fall out of regulation.
Active
t [ms]
L < L B ? ?
V in
[V]
V in
PFC
Disable
FET
V gs
L = L B
L > L B ? ?
t [ms]
Figure 14. Burst Mode
5.4 Output Power and PFC Boost Inductor
In normal operating mode, the nominal output power is
estimated by the following equation:
90 265
V AC(rms)
Figure 15. Relative Effects of Varying Boost Inductance
5.5 PFC Output Capacitor
2 V link – ? V in ? min ? ? 2 ?
2 ? f max ? L B ? V link
P o = ? ? ? ? ? V in ? min ? ? ? ---------------------------------------------------------
where:
[Eq.1]
The value of the PFC output capacitor needs to be selected
based upon voltage ripple and hold-up requirements. To
ensure system stability with the digital controller, the
recommended value of the capacitor is within the range of
0.5 ? F/watt to 2.0 ? F/watt with a V link voltage of 400V.
P o
?
rated output power of the system
efficiency of the boost converter (estimated as 100%
by the PFC algorithm)
5.6 Output IFB Sense and Input IAC Sense
A current proportional to the PFC output voltage, V link , is
supplied to the IC on pin IFB and is used as a feedback control
R6
V in(min) minimum RMS line voltage is 90V, measured after
the rectifier and EMI filter
V link nominal PFC output voltage (must be 400V)
f max maximum switching frequency is 70kHz
L B boost inductor specified by rated power requirement
? <1 margin factor to guarantee rated output power (P o )
against boost inductor tolerances.
Equation 1 is provided for explanation purposes only. Using
substituted required design values for V link and f max gives the
following equation:
signal. This current is compared against an internal
fixed-value reference current.
The ADC is used to measure the magnitude of the I IFB current
through resistor R IFB . The magnitude of the I IFB current is then
compared to an internal reference current (I ref ) of 129 ? A.
V link
R5
I FB R IFB
V DD
8
CS1501
P o = ? ? ? ? ? 90V ? ? -------------------------------------------------------------
2 400V – ? 90V ? 2 ?
2 ? 70kHz ? L B ? 400V
[Eq.2]
IFB
1
15k
24k
ADC
I ref
Changing the value for the V link voltage is not recommended.
10
Figure 16. IFB Input Pin Model
DS927F4
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