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| 型号： | CS1501-FSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC PFC CONTROLLER DCM OCP 8SOIC |
| 产品变化通告： | CS1501, 1601 Datasheet Update Change 11/Jan/2012 |
| 设计资源： | CS150x/160x PCB Layout Guidelines Driving Mosfets with CS1501/1601 CS1501/1601 Driving ZCD Pin from Mosfet Drain |
| 特色产品： | CS1501/CS1601 Power Factor Correction IC Controllers |
| 标准包装： | 100 |
| 模式： | 临界传导（CRM），间歇导电（DCM） |
| 频率 - 开关： | 70kHz |
| 电流 - 启动： | 68µA |
| 电源电压： | 7.9 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 散装 |
| 其它名称： | 598-1912 |
CS1501
1. INTRODUCTION
V DD
V DD
600k
Voltage
Regulator
8
VDD
STBY
2
V DD
POR
+
-
V DD ( on)
V Z
V DD ( off)
15k
I ref
IFB
1
24k
ADC
V DD
IAC
3
15k
24k
ADC
I ref
7
GD
t LEB
t ZCB
6
GND
CS
4
600
V CS (th)
-
+
CS
Threshold
+
V CS (clamp ) -
CS Clamp
Zero Crossing
Detect
+
-
V ZCD(th )
5
ZCD
Figure 1. CS1501 Block Diagram
The CS1501 digital power factor correction (PFC) control IC is
designed to deliver the lowest system cost by reducing the
total number of system components and optimizing the EMI
noise signature, which reduces the conducted EMI filter
requirements. The CS1501 digital algorithm determines the
behavior of the boost converter during startup, normal
the PFC active-switching behavior and efficiency. The
auxiliary voltage is normalized using an external attenuator
and is connected to the ZCD pin, providing the CS1501 a
mechanism to detect the valley/zero crossings. The ZCD
comparator looks for the zero crossing on the auxiliary winding
and switches when the auxiliary voltage is below zero.
operation, and under fault
conditions (overvoltage,
Switching in the valley of the oscillation minimizes the
overcurrent, and overtemperature).
The PFC processor logic regulates the power transfer by
using an adaptive digital algorithm to optimize the PFC
active-switch (MOSFET) drive signal duty cycle and switching
frequency. The adaptive controller uses independent
analog-to-digital converter (ADC) channels when sensing the
feedback and feedforward analog signals required to
implement the digital PFC control algorithm.
The AC mains rectified voltage (on pin IAC) and PFC output
link voltage (on pin IFB) are transformed by the PFC
processor logic and used to generate the optimum PFC
active-switch drive signal (GD) by calculating the optimal
switching frequency and t ON time on a cycle-by-cycle basis.
An auxiliary winding is typically added to the PFC boost
inductor to provide zero-current detection (ZCD) information.
The ZCD acts as a demagnetization sensor used to monitor
2
switching losses and reduces EMI noise.
The PFC controller uses a current sensor for overcurrent
protection. The boost inductor peak current is measured
across an external resistor in the switching circuit on a
cycle-by-cycle basis. An overcurrent fault is generated when
the sense voltage applied to the CS pin exceeds a predefined
reference voltage.
The CS1501 includes a supervisor and protection circuit to
manage startup, shutdown, and fault conditions. The
protection circuit is designed to prevent output overvoltage as
a result of load and AC mains transients. The PFC power
converter main rectified voltage (V rect ) and output link voltage
(V link ) are monitored for overvoltage faults which would lead to
shutdown of the PFC controller. The PFC overvoltage
protection is designed for auto-recovery; operation resumes
once the fault clears.
DS927F4
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