参数资料
型号: CS4205-KQZ
厂商: Cirrus Logic Inc
文件页数: 71/81页
文件大小: 0K
描述: IC CODEC AC97 I2S 48-LQFP
标准包装: 250
类型: 音频编解码器 '97
数据接口: 串行
分辨率(位): 18,20 b
ADC / DAC 数量: 1 / 2
三角积分调变:
动态范围,标准 ADC / DAC (db): 90 / 90
电压 - 电源,模拟: 4.75 V ~ 5.25 V
电压 - 电源,数字: 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-TQFP(9x9)
包装: 托盘
产品目录页面: 754 (CN2011-ZH PDF)
其它名称: 598-1182
CS4205
DS489PP4
73
AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29
This pin needs a 1000 pF NPO capacitor connected to analog ground.
AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30
This pin needs a 1000 pF NPO capacitor connected to analog ground.
AFLT3 - Mic ADC Channel Antialiasing Filter, Input, Pin 31
This pin needs a 1000 pF NPO capacitor connected to analog ground.
AC-Link Pins
RESET# - AC ’97 Chip Reset, Input, Pin 11
This active low signal is the asynchronous Cold Reset input to the CS4205. The CS4205 must be reset
before it can enter normal operating mode.
SYNC - AC-Link Serial Port Sync Pulse, Input, Pin 10
SYNC is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample
rate, 48 kHz. The signal is generated by the controller and is synchronous to BIT_CLK. SYNC is an
asynchronous input when the CS4205 is configured as a primary codec and is in a PR4 powerdown
state. A series terminating resistor of 47
should be connected on this signal close to the controller.
BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6
This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a
12.288 MHz output clock derived from either a 24.576 MHz crystal or from the internal PLL based on
the XTL_IN input clock. When the CS4205 is in secondary mode, this signal is an input which controls
the AC-link serial interface and generates all internal clocking including the AC-link serial interface
timing and the analog sampling clocks. A series terminating resistor of 47
should be connected on
this signal close to the CS4205 in primary mode or close to the BIT_CLK source in secondary mode.
SDATA_OUT - AC-Link Serial Data Input Stream to AC ’97, Input, Pin 5
This input signal receives the control information and digital audio output streams. The data is clocked
into the CS4205 on the falling edge of BIT_CLK. A series terminating resistor of 47
should be
connected on this signal close to the controller.
SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8
This output signal transmits the status information and digital audio input streams from the ADCs. The
data is clocked out of the CS4205 on the rising edge of BIT_CLK. A series terminating resistor of 47
should be connected on this signal close to the CS4205.
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