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| 型号： | CS4210VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | IEEE 1394 OHCI Controller |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 12/102页 |
| 文件大小： | 1571K |
| 代理商： | CS4210VJG |
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12
Revision 1.0
G
Signal Definitions
(Continued)
2.2
SIGNAL DESCRIPTIONS
2.2.1
PCI Bus Interface Signals
Signal Name
Pin No.
Type
Description
AD[31:0]
Refer to
Table 2-3
I/O
Multiplexed Address and Data
AD[31:0] is a physical address during the first clock of a PCI transaction; it is
the data during subsequent clocks.
When the CS4210 is a PCI master, AD[31:0] are outputs during the address
and write data phases, and are inputs during the read data phase of a trans-
action.
When the CS4210 is a PCI slave, AD[31:0] are inputs during the address
and write data phases, and are outputs during the read data phase of a
transaction.
C/BE[3:0]#
65, 53, 41,
28
I/O
Bus Command and Byte Enables
Multiplexed bus command and byte enables.
FRAME#
43
I/O
Cycle Frame
Driven by the initiator to indicate the beginning and duration of an access.
IRDY#
44
I/O
Initiator Ready
Indicates that the initiator is ready to complete the current data phase of the
transaction.
TRDY#
45
I/O
Target Ready
Indicates that the current data phase of the transaction is ready to be com-
pleted.
STOP#
48
I/O
Stop
Indicates that the current target is requesting the initiator to stop the current
transaction.
DEVSEL#
47
I/O
Device Select
When actively driven, DEVSEL# indicates the driving device has decoded
its address as the target of the current access.
IDSEL
29
I
Initialization Device Select
Used as a chip select during configuration read and write transactions.
PERR#
49
I/O
Parity Error
Used for reporting data parity errors during all PCI transactions except a
Special Cycle.
SERR#
51
I/O
System Error
Used for reporting address parity errors, data parity errors on the Special
Cycle command, or any other system error where the result will be cata-
strophic.
PAR
52
I/O
Parity
PAR is even parity across AD[31:0] and C/BE[3:0]. PAR is an input when
AD[31:0] are inputs and is an output when AD[31:0] are outputs.
PREQ#
15
O
PCI Bus Request
PCI bus request to PCI bus arbiter.
PGNT#
14
I
PCI Bus Grant
PCI bus grant from PCI bus arbiter.
INTA#
8
O
Interrupt A
1394 OpenHCI PCI interrupt.
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相关代理商/技术参数 |
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| CS4215 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16-Bit Multimedia Audio Codec |
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