- 您现在的位置：买卖IC网 > PDF目录380066 > CS4210VJG (NATIONAL SEMICONDUCTOR CORP) IEEE 1394 OHCI Controller PDF资料下载
参数资料
| 型号： | CS4210VJG |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | IEEE 1394 OHCI Controller |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 13/102页 |
| 文件大小： | 1571K |
| 代理商： | CS4210VJG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页
Revision 1.0
13
www.national.com
G
Signal Definitions
(Continued)
RST#
10
I
PCI Reset
RST# is driven low to reset the device.
PCLK
12
I
Clock
0-33 MHz PCI clock.
PME#
17
O
Power Management Event
PCI power management pin as defined in the PCI Bus Power Management
Specification Revision 1.1.
2.2.2
PHY-Link Interface Signals
Signal Name
Pin No.
I/O
Description
DATA[0:7]
81, 82, 84,
85, 86, 88,
89, 90
I/O
PHY Data
Bidirectional data lines driven by both the Link and PHY layer modules. The
width of the data bus depends on the speed of data transfer rate. Packet rate
for 100 Mbit/sec transfers use DATA[0:1], 200 Mbit/sec transfers use
DATA[0:3], 400 Mbit/sec transfers use DATA[0:7].
Note:
DATA0 is considered the MSB (most significant bit) based upon the
IEEE 1394-1995 specification.
CTRL[0:1]
93, 92
I/O
Control bits 1 and 0
Bidirectional handshaking signals driven by both the Link and PHY layer
modules. The CS4210 and CS4103 use these signals to arbitrate the control
of the PHY-Link interface. The control bits also indicate the type of transfer
communicating between the two layers namely idle, status, receive, and
transmit.
LREQ
97
O
Link Request
Used by the CS4210 to request access of the 1394 bus and to read/write the
internal registers of the CS4103.
SCLK
95
I
Sync Clock
The 49.152 MHz clock input driven by the CS4103’s PLL block synchronized
to the 1394 bus clock. This clock is also used to synchronize the LREQ,
CTRL[0:1], and DATA[0:7] communication protocol between the CS4210
and CS4103.
LPS
99
O
Link Power Status
Indicates the power status of the CS4210. If LPS is low indicating the
CS4210 is not powered, the signals CTRL[0:1], DATA[0:7], and SCLK con-
nected to the CS4210 are disabled.
LNKON
98
I
Link On
Indicates to the CS4210 that the CS4103 has received a Link-On packet
addressed to this node.
DIRECT
79
I
Direct
High indicates direct connection. Low indicates isolation barrier. Set high
when using the single capacitor bus hold isolation.
2.2.1
PCI Bus Interface Signals (Continued)
Signal Name
Pin No.
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| CS4215-KL | 16-Bit Multimedia Audio Codec |
| CS4215-KQ | 16-Bit Multimedia Audio Codec |
| CS4215 | 16-Bit Multimedia Audio Codec |
| CS4216 | 16-Bit Stereo Audio Codec |
| CS4216-KL | IC EEPROM SRL 256-8BIT 8DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4211-4 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Optoelectronic |
| CS4211-KM | 制造商:CRISTAL 功能描述:4211-KM |
| CS4212-KL | 制造商: 功能描述:4212KL |
| CS4213GP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:摩托车点火器电路 =MB4213 |
| CS4215 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16-Bit Multimedia Audio Codec |
发布紧急采购，3分钟左右您将得到回复。