参数资料
型号: CS4265-CNZ
厂商: Cirrus Logic Inc
文件页数: 37/46页
文件大小: 0K
描述: IC CODEC 24BIT 104DB 32QFN
标准包装: 60
类型: 立体声音频
数据接口: PCM 音频接口
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
动态范围,标准 ADC / DAC (db): 104 / 104
电压 - 电源,模拟: 3.13 V ~ 5.25 V
电压 - 电源,数字: 3.13 V ~ 5.25 V
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-QFN
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 托盘
产品目录页面: 754 (CN2011-ZH PDF)
配用: 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
其它名称: 598-1039
42
DS657F3
CS4265
6.11
DAC Channel B Volume Control - Address 0Bh
6.11.1
Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB.
The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits
activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as
shown in Table 16. The volume changes are implemented as dictated by the DACSoft and DACZero-
Cross bits in the DAC Control 2 register (see Section 6.12.1).
6.12
DAC Control 2 - Address 0Ch
6.12.1
DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 17.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zerocrossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
76
543
21
0
Vol7
Vol6
Vol5
Vol4
Vol3
Vol2
Vol1
Vol0
Binary Code
Volume Setting
00000000
0 dB
00000001
-0.5 dB
00101000
-20 dB
00101001
-20.5 dB
11111110
-127 dB
11111111
-127.5 dB
Table 16. Digital Volume Control Example Settings
76
543
21
0
DACSoft
DACZero
InvertDAC
Reserved
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CS4265-CNZ/C1 制造商:Cirrus Logic 功能描述:
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CS4267AM 制造商:Rochester Electronics LLC 功能描述:- Bulk