参数资料
型号: CS4360-DZZ
厂商: Cirrus Logic Inc
文件页数: 9/37页
文件大小: 0K
描述: IC DAC STER 6CH 102DB 28TSSOP
标准包装: 50
位数: 24
数据接口: 串行
转换器数目: 6
电压电源: 模拟和数字
功率耗散(最大): 265mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
输出数目和类型: 6 电压,单极
采样率(每秒): 192k
其它名称: 598-1056-5
CS4360
DS517F2
17
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Inputs: Logic 0 = GND, Logic 1 = VLC
Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
9.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode.
Parameter
Symbol
Min
Max
Unit
IC Mode
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
s
Clock Low time
tlow
4.7
-
s
Clock High Time
thigh
4.0
-
s
Setup Time for Repeated Start Condition
tsust
4.7
-
s
SDA Hold Time from SCL Falling
(Note 7)
thdd
0-
s
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-1
s
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
s
Acknowledge Delay from SCL Falling
(Note 8)
tack
-
ns
5
256
Fs
×
---------------------
5
128
Fs
×
---------------------
5
64Fs
×
------------------
t
buf
t
hds t
t
lo w
t
hd d
t
high
t
su d
Sto p
S t a r t
SD A
SC L
t
irs
RS T
t
hdst
t
rc
t
fc
t sust
t susp
St a r t
Sto p
R e pe at e d
t
rd
t
fd
t
ac k
Figure 13. Control Port Timing - IC Mode
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