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参数资料
| 型号： | CS5461A-ISZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 17/44页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 24SSOP |
| 标准包装： | 1,000 |
| 输入阻抗： | 30 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 0.8V |
| 电压 - 低输入/输出： | 0.2V |
| 电流 - 电源： | 2.9mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 带卷 (TR) |
| 配用： | 598-1552-ND - BOARD EVAL & SOFTWARE CS5461A |
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CS5461A
E1 ...
E2 ...
t PW
FREQ E
...
...
Figure 4. Alternate Pulse Format on E1 and E2
is (MCLK/K)/16. The pulse duration (t dur ) is an integer
multiple of MCLK cycles, approximately equal to:
and E2 output pins when full-scale input signals are ap-
plied to the voltage and current channels, then:
? --------------------------------------------
? ------------
PW
t dur ? sec ?
1
PulseRateE 1 , 2 ? 8
PulseRateE 1 , 2
t
1
The pulse frequency (FREQ E ) is determined by the
----------------------------------- ? t dur ? sec ? ? -----------------------------------------
The maximum pulse duration (t dur ) is determined by the
sampling rate and the minimum is defined by the maxi-
mum pulse frequency. The t dur limits are:
1 1
(MCLK/K)/16 ? 8 (MCLK/K)/1024 ? 8
The Pulse Width Register (PW) does not affect the nor-
mal format.
5.4.2 Alternate Pulse Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and ALT = 1 in the Configuration Register con-
figures the E1 and E2 pins for alternating pulse format
output (see Figure 4 ). Each pin produces alternating ac-
tive-low pulses with a pulse duration (t PW ) defined by
the Pulse Width Register (PW):
PulseRateE 1,2 Register and can be calculated using the
transfer function. The energy direction is not defined in
the alternate pulse format.
5.4.3 Mechanical Counter Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
enables E1 and E2 for mechanical counters and similar
discrete counting instruments. When energy is nega-
tive, pulses appear on E2 (see Figure 5). When energy
is positive, the pulses appear on E1. The pulse width is
defined by the Pulsewidth Register and will limit the out-
put pulse frequency (FREQ E ). By default, PW = 512
samples, if MCLK = 4.096 MHz and K = 1 then
t PW = 128 ms. To ensure that pulses will occur, the
PulseRateE 1,2 Register must be set to an appropriate
value.
-----------------------------------------
t PW ? ms ?
=
PW
(MCLK/K)/1024
5.4.4 Stepper Motor Format
Setting bits STEP = 1 and MECH = 0 in the Control
If MCLK = 4.096 MHz, K = 1, and PW = 1 then
t PW = 0.25 ms. To ensure that pulses occur on the E1
Register and bit ALT = 0 in the Configuration Register
configures the E1 and E2 pins for stepper motor format.
When the accumulated active power equals the defined
FREQ E
t PW
E1
...
...
E2
...
Positive Energy
Negative Energy
...
Figure 5. Mechanical Counter Format on E1 and E2
DS661F3
17
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5461-IS | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Single Phase Bi-Directional Power/Energy IC |
| CS5461-ISZ | 制造商:Cirrus Logic 功能描述:PWR MEASUREMENT 24SSOP - Rail/Tube |
| CS5461-ISZR | 制造商:Cirrus Logic 功能描述:PWR MEASUREMENT 24SSOP - Tape and Reel |
| CS5462 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:LOW COST POWER ENERGY IC WITH PULSE OUTPUT |
| CS5462-IS | 功能描述:电流和电力监控器、调节器 Low-Cost Pwr/Energy w/Pulse Output IC RoHS:否 制造商:STMicroelectronics 产品:Current Regulators 电源电压-最大:48 V 电源电压-最小:5.5 V 工作温度范围:- 40 C to + 150 C 安装风格:SMD/SMT 封装 / 箱体:HPSO-8 封装:Reel |
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