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参数资料
| 型号： | CS8416-CNZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 5/37页 |
| 文件大小： | 0K |
| 描述： | IC RCVR DGTL 192KHZ 28QFN COMM |
| 标准包装： | 490 |
| 类型： | 数字音频接口接收器 |
| 应用： | 数字音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-QFN |
| 供应商设备封装： | 28-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 配用： | 598-1017-ND - BOARD EVAL FOR CS8416 RCVR |
| 其它名称： | 598-1723 |
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DS578F3
13
CS8416
RXN
5
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single-
ended operation this should be AC coupled to ground through a capacitor. See “External
AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits.
OMCK
25
System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the
Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock.
OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System
RMCK
24
Input Section Recovered Master Clock (Output) - Input section recovered master clock output from
the PLL. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x through the RMCKF bit
in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4
register (04h).
OSCLK
27
Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK
28
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
SDOUT
26
Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL
through a 47 k
Ω resistor to place the part in Software Mode.
SDA /
CDOUT
17
Serial Control Data I/O (IC) / Data Out (SPI) (Input/Output) - In IC Mode, SDA is the control I/O data
line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-
put data from the control port interface on the CS8416. See the “Control Port Description” section on
SCL /
CCLK
16
Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the
AD0 / CS
14
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416
into SPI Control Port Mode. With no falling edge, the CS8416 defaults to IC Mode. In IC Mode, AD0 is
a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the
AD1 /
CDIN
15
Address Bit 1 (IC) / Serial Control Data in (SPI) (Input) - In IC Mode, AD1 is a chip address pin. In
SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description”
AD2 /
GPO2
18
General Purpose Output 2 (Output) - If using the IC control port, this pin must be pulled high or low
through a 47 k
Ω resistor. See the “Control Port Description” section on page 33 and “General Purpose
Outputs” on page 29 for GPO functions.
GPO1
19
General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.
GPO0
20
General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions.
Pin
Name
Pin #
Pin Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8416-CNZ | 制造商:Cirrus Logic 功能描述:Receiver IC RoHS Compliant:Yes |
| CS8416-CNZR | 功能描述:音频发送器、接收器、收发器 IC 192 kHz Digital Audio Receiver RoHS:否 制造商:Cirrus Logic 工作电源电压:3.3 V, 5 V 电源电流:11.8 mA 通道数量:1 最大工作温度:+ 70 C 接口类型:I2C, SPI 安装风格:SMD/SMT 封装 / 箱体:TSSOP-28 封装: |
| CS8416-CS | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER |
| CS8416-CSR | 制造商:Cirrus Logic 功能描述:- Tape and Reel |
| CS8416CSZ | 制造商:Cirrus Logic 功能描述: |
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