参数资料
| 型号： | CS8416-DZZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 31/37页 |
| 文件大小： | 0K |
| 描述： | IC RCVR DGTL 192KHZ 28TSSOP AUTO |
| 标准包装： | 50 |
| 类型： | 数字音频接口接收器 |
| 应用： | 数字音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 配用： | 598-1017-ND - BOARD EVAL FOR CS8416 RCVR |
| 其它名称： | 598-1726 |
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DS578F3
37
CS8416
1 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, but
increased wide-band jitter. Use this setting for the best performance when the output is connected to a delta-
sigma digital-to-analog converter (DAC).
TRUNC
– Determines if the audio word length is set according to the incoming channel status data as de-
coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0].
Default = ‘0’
0 – Incoming data is not truncated.
1 – Incoming data is truncated according to the length specified in the channel status data.
Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data if de-emphasis filter
is not used.
Reserved
– These bits may change state depending on the input audio data.
14.3 Control1 (01h)
SWCLK
- Lets OMCK determine RMCK, OSCLK, OLRCK when PLL loses lock
Default = ‘0’
0 - Disable automatic clock switching. RMCK runs at the VCO frequency (~750 kHz) on PLL Unlock.
1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on
PLL Unlock.
MUTESAO
- Mute control for the serial audio output port
Default = ‘0’
0 - SDOUT not muted.
1 – SDOUT muted (set to all zeros).
INT[1:0]
- Interrupt output pin (INT) control
Default = ‘00’
00 - Active high; high output indicates interrupt condition has occurred.
01 - Active low, low output indicates an interrupt condition has occurred.
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Thus it is not recommended
to multiplex INT onto GPO2 in IC Control Port Mode since an external resistor is required on GPO2 to spec-
ify the AD2 bit of the chip address.
11 – Reserved.
HOLD[1:0]
– Determine how received audio sample is affected when a receive error occurs
Default = ‘00’
00 – hold last audio sample.
01 – replace the current audio sample with all zeros (mute).
10- do not change the received audio sample.
11 - reserved
76543210
SWCLK
MUTESAO
INT1
INT0
HOLD1
HOLD0
RMCKF
CHS
相关PDF资料 |
PDF描述 |
|---|---|
| CS8420-DSZ | IC CONV S/R DGTL AUDIO 28-SOIC |
| CS8421-CNZ | IC SAMPLE RATE CONVERTER 20QFN |
| CS8427-DZZ | IC TXRX DGTL AUDIO 96KHZ 28TSSOP |
| CY28329ZXC | IC CLOCK CK408B PLUMAS 56SSOP |
| CY28346OXC | IC CLOCK DIFF OUT CK408 56SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8416-DZZR | 功能描述:音频发送器、接收器、收发器 IC 192 kHz Digital Audio Receiver RoHS:否 制造商:Cirrus Logic 工作电源电压:3.3 V, 5 V 电源电流:11.8 mA 通道数量:1 最大工作温度:+ 70 C 接口类型:I2C, SPI 安装风格:SMD/SMT 封装 / 箱体:TSSOP-28 封装: |
| CS8416-IS | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER |
| CS8416-IZ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER |
| CS841A1 | 制造商:HVPSI 制造商全称:High Voltage Power Solutions, Inc. 功能描述:MOV Modules |
| CS841A2 | 制造商:HVPSI 制造商全称:High Voltage Power Solutions, Inc. 功能描述:MOV Modules |
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