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| 型号： | CY22150ZI |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator |
| 中文描述： | 一个锁相环通用闪存可编程和2线串行可编程时钟发生器 |
| 文件页数： | 10/13页 |
| 文件大小： | 211K |
| 代理商： | CY22150ZI |
CY22150
Document #: 38-07104 Rev. *F
Page 10 of 13
Table 14. Absolute Maximum Conditions
Parameter
V
DD
V
DDL
T
S
T
J
Description
Min.
–0.5
–0.5
–65
Max.
7.0
7.0
125
125
450
380
Unit
V
V
°C
°C
mW
mW
V
V
V
V
Supply Voltage
I/O Supply Voltage
Storage Temperature
[2]
Junction Temperature
Package Power Dissipation – Commercial Temp
Package Power Dissipation – Industrial Temp
Digital Inputs
Digital Outputs referred to V
DD
Digital Outputs referred to V
DDL
Static Discharge Voltage per MIL-STD-833, Method 3015
AV
SS
– 0.3
V
SS
– 0.3
V
SS
– 0.3
AV
DD
+ 0.3
V
DD
+ 0.3
V
DDL
+0.3
2000
ESD
Table 15. Recommended Operating Conditions
Parameter
V
DD
VDDL
HI[3]
VDDL
LO[3]
T
AC
T
AI
C
LOAD
C
LOAD
f
REFD
f
REFC
t
PU
Description
Min.
3.135
3.135
2.375
0
–40
Typ.
3.3
3.3
2.5
Max.
3.465
3.465
2.625
70
85
15
15
133
30
500
Unit
V
V
V
°C
°C
pF
pF
MHz
MHz
ms
Operating Voltage
Operating Voltage
Operating Voltage
Ambient Commercial Temp
Ambient Industrial Temp
Max. Load Capacitance, V
DD
/V
DDL
= 3.3V
Max. Load Capacitance, V
DDL
= 2.5V
Driven REF
Crystal REF
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be
monotonic)
1
8
0.05
Table 16. DC Electrical Characteristics
Parameter
[4]
I
OH3.3
Output High Current
I
OL3.3
Output Low Current
I
OH2.5
Output High Current
I
OL2.5
Output Low Current
V
IH
Input High Voltage
V
IL
Input Low Voltage
C
IN
Input Capacitance
I
IZ
Input Leakage Current
V
HYS
Hysteresis of Schmitt
triggered inputs
I
VDD[5,6]
Supply Current
I
VDDL3.3[5,6]
Supply Current
I
VDDL2.5[5,6]
Supply Current
Notes:
2.
Rated for 10 years.
3.
V
is only specified and characterized at 3.3V ± 5% and 2.5V ± 5%. V
DDL
may be powered at any value between 3.465V and 2.375V.
4.
Not 100% tested.
5.
I
currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz.
6.
Use CyClocksRT to calculate actual I
VDD
and I
VDDL
for specific output frequency configurations.
Name
Description
Min.
12
12
8
8
0.7
Typ.
24
24
16
16
Max.
Unit
mA
mA
mA
mA
V
DD
V
DD
pF
μ
A
V
DD
V
OH
= V
DD
– 0.5, V
DD
/V
DDL
= 3.3V (sink)
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V (source)
V
OH
= V
DDL
– 0.5, V
DDL
= 2.5V (source)
V
OL
= 0.5, V
DDL
= 2.5V (sink)
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
SCLK and SDAT Pins
SCLK and SDAT Pins
SCLK and SDAT Pins
0.3
7
5
0.05
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
= 3.465V)
V
DDL
Current (V
DDL
= 2.625V)
45
25
17
mA
mA
mA
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