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| 型号： | CY22150ZI |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator |
| 中文描述： | 一个锁相环通用闪存可编程和2线串行可编程时钟发生器 |
| 文件页数： | 11/13页 |
| 文件大小： | 211K |
| 代理商： | CY22150ZI |
CY22150
Document #: 38-07104 Rev. *F
Page 11 of 13
Table 17. AC Electrical Characteristics
Parameter
[7]
t1
Output Frequency,
Commercial Temp
Name
Description
Min.
Typ.
Max.
200
166.6
166.6
150
55
Unit
MHz
MHz
MHz
MHz
%
Clock output limit, 3.3V
Clock output limit, 2.5V
Clock output limit, 3.3V
Clock output limit, 2.5V
Duty cycle is defined in
Figure 6
; t1/t2
fOUT < 166 MHz, 50% of V
DD
Duty cycle is defined in
Figure 6
; t1/t2
fOUT > 166 MHz, 50% of V
DD
Output clock rise time, 20% – 80% of V
DDL
.
Defined in
Figure 7
.
Output dlock fall time, 80% – 20% of V
DDL
.
Defined in
Figure 7
.
Output dlock rise time, 20% – 80% of
V
DD
/V
DDL
. Defined in
Figure 7
.
Output dlock fall time, 80% – 20% of
V
DD
/V
DDL
. Defined in
Figure 7
.
Output-output skew between related outputs.
Peak-to-peak period jitter
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
45
Output Frequency,
Industrial Temp
t2
LO
Output Duty Cycle
50
t2
HI
Output Duty Cycle
40
50
60
%
t3
LO
Rising Edge Slew
Rate (V
DDL
= 2.5V)
Falling Edge Slew
Rate (V
DDL
= 2.5V)
Rising Edge Slew
Rate (V
DDL
= 3.3V)
Falling Edge Slew
Rate (V
DDL
= 3.3V)
Skew
Clock Jitter
PLL Lock Time
0.6
1.2
V/ns
t4
LO
0.6
1.2
V/ns
t3
HI
0.8
1.4
V/ns
t4
HI
0.8
1.4
V/ns
t5
[8]
t6
[9]
t10
250
ps
ps
ms
250
0.30
3
Device Characteristics
Parameter
θ
JA
Complexity
Name
theta JA
Value
115
74,600
Unit
°C/W
transistors
Transistor Count
Ordering Information
Ordering Code
CY22150FC
CY22150FI
CY22150ZC-xxx
[10]
CY22150ZI-xxx
[10]
CY3672
CY3672ADP000
Package Name
Z16
Z16
Z16
Z16
FTG Development System
CY22150F Socket
Package Type
16-lead TSSOP
16-lead TSSOP
16-lead TSSOP
16-lead TSSOP
N/A
Operating Range
Commercial (0 to 70°C)
Industrial (–40 to 85°C)
Commercial (0 to 70°C)
Industrial (–40 to 85°C)
Operating Voltage
3.3V
3.3V
3.3V
3.3V
Notes:
7.
8.
9.
Not 100% tested, guaranteed by design.
Skew value guaranteed when outputs are generated from the same divider bank. See Logic Diagram for more information.
Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, V
, (2.5V or 3.3V jitter in
“
PLL-Based Systems: Causes, Effects, and Solutions
,” available at http://wwww.cypress.com/clock/appnotes.html, or contact your local Cypress field appli-
cations engineer).
10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of
100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative.
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相关代理商/技术参数 |
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|---|---|
| CY22150ZI-304 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY22150ZIT | 制造商:Cypress Semiconductor 功能描述: |
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| CY22150ZXC-XXX | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator |
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