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参数资料
| 型号： | CY28445LFXC-5T |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 12/25页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 68QFN |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | LVTTL，晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:22 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-VFQFN 裸露焊盘 |
| 供应商设备封装： | 68-QFN（8x8） |
| 包装： | 带卷 (TR) |
CY28445-5
....................... Document #: 38-07739 Rev *C Page 2 of 25
Pin Descriptions
Pin No.
Name
Type
Description
1
PCIF1
O, SE 33 MHz clock output
2
VTT_PWRGD#/PD
I, PD
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS[C:A],
ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW)
assertion, this pin becomes a real-time input for asserting power-down (active
HIGH).
3
VDD48
PWR
3.3V power supply.
4
FSA/48M
I/O
3.3V-tolerant input for CPU frequency selection / Fixed 48 MHz clock output.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications.
5
VSS48
GND
Ground.
6, 7
DOT96T/27M_non
spread
DOT96C/27M_Spread
O, DIF Fixed 96 MHz differential clock output / Single ended 27 MHz clock outputs.
When configured for 27 MHz, only the clock on pin 7contains spread.
Selected via FCTSEL[0:1] at VTT_PWRGD# assertion.
8FSB
I
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications
9, 20, 25, 34,
59, 60
CLKREQ#[1], [3:6], [8]
I, PU
3.3V LVTTL input for enabling assigned SRC clock (active LOW)
10, 11
SRC[T/C]0/
LCD100M[T/C]
O,DIF 100 MHz differential serial reference clock output / 100 MHz LVDS differ-
ential clock output.
Selected via FCTSEL[0:1] at VTT_PWRGD# assertion
12, 17, 28, 35 VDD_SRC
PWR
3.3V power supply
13,14, 15,
16, 18, 19,
21, 22, 23,
24, 26, 27,
29, 30, 32,
33,
SRC[T/C][1:8]
O, DIF 100 MHz differential serial reference clock outputs.
31
VSS_SRC
GND
Ground.
36, 37
CPUT2_ITP/SRCT10,
CPUC2_ITP/SRCC10
O, DIF Selectable differential CPU / SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC10 (default)
ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP
38
VDDA
PWR
3.3V power supply for PLL.
39
VSSA
GND
Ground for PLL.
40
IREF
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
41, 42, 44, 45 CPU[T/C][0:1]
O, DIF Differential CPU clock outputs.
43
VDD_CPU
PWR
3.3V power supply
46
VSS_CPU
GND
Ground
47
SCLK
I
SMBus-compatible SCLOCK.
48
SDATA
I/O, OD SMBus-compatible SDATA.
49
VDD_REF
PWR
3.3V power supply
50
XOUT
O, SE 14.318 MHz crystal output.
51
XIN
I
14.318 MHz crystal input.
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