- 您现在的位置：买卖IC网 > PDF目录170346 > CY39050V484-222MBC (CYPRESS SEMICONDUCTOR CORP) LOADABLE PLD, 7 ns, PBGA484 PDF资料下载
参数资料
| 型号： | CY39050V484-222MBC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 7 ns, PBGA484 |
| 封装： | 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484 |
| 文件页数： | 6/57页 |
| 文件大小： | 1166K |
| 代理商： | CY39050V484-222MBC |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 14 of 57
IEEE 1149.1 Compliant JTAG Operation
The Delta39K family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Boundary Scan
The Delta39K family supports Bypass, Sample/Preload, Ex-
test, Intest, Idcode and Usercode boundary scan instructions.
The JTAG interface is shown in Figure 11.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Delta39K family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Configuration
Each device of the Delta39K family is available in a volatile and
a Self-Boot package. Cypress’s CPLD boot EEPROM is used
to store configuration data for the volatile solution and an em-
bedded on-chip FLASH memory device is used for the Self-
Boot solution.
For volatile Delta39K packages, programming is defined as
the loading of a user’s design into the external CPLD boot
EEPROM. For Self-Boot Delta39K packages, programming is
defined as the loading of a user’s design into the on-chip
FLASH internal to the Delta39K package. Configuration is de-
fined as the loading of a user’s design into the Delta39K die.
Configuration can begin in two ways. It can be initiated by tog-
gling the Reconfig pin from LOW to HIGH, or by issuing the
appropriate IEEE std 1149.1 JTAG instruction to the Delta39K
device via the JTAG interface. There are two IEEE std 1149.1
JTAG instructions that initiate configuration of the Delta39K.
The Self Config instruction causes the Delta39K to (re)config-
ure with data stored in the serial boot PROM or the embedded
FLASH memory. The Load Config instruction causes the
Delta39K to (re)configure according to data provided by other
sources such as a PC, automatic test equipment (ATE), or an
embedded micro-controller/processor via the JTAG interface.
For more information on configuring Delta39K devices, refer
to
the
application
note
titled
“Configuring
Delta39K/Quantum38K”
application
note
at
http://www.cypress.com.
There are two configuration options available for issuing the
IEEE std 1149.1 JTAG instructions to the Delta39K. The first
method is to use a PC with the C3ISR programming cable and
software. With this method, the ISR pins of the Delta39K de-
vices in the system are routed to a connector at the edge of
the printed circuit board. The C3ISR programming cable is
then connected between the PC and this connector. A simple
configuration file instructs the ISR software of the program-
ming operations to be performed on the Delta39K devices in
the system. The ISR software then automatically completes all
of the necessary data manipulations required to accomplish
configuration, reading, verifying, and other ISR functions. For
more information on the Cypress ISR interface, see the ISR
Programming Kit data sheet (CY3900i).
The second configuration option for the Delta39K is to utilize
the embedded controller or processor that already exists in the
system. The Delta39K ISR software assists in this method by
converting the device HEX file into the ISR serial stream that
contains the ISR instruction information and the addresses
and data of locations to be configured. The embedded control-
ler then simply directs this ISR stream to the chain of Delta39K
devices to complete the desired reconfiguration or diagnostic
operations. Contact your local sales office for information on
availability of this option.
Programming
The on-chip FLASH device of the Delta39K Self-Boot package
is programmed by issuing the appropriate IEEE std 1149.1
JTAG instruction to the internal FLASH memory via the JTAG
interface. This can be done automatically using ISR/STAPL
software. The configuration bits are sent from a PC through
the JTAG port into the Delta39K via the C3ISR programming
cable. The data is then internally passed from Delta39K to the
on-chip FLASH. For more information on how to program the
Delta39K through ISR/STAPL, please refer to the ISR/STAPL
User Guide.
The external CPLD boot EEPROM used to store configuration
data for the Delta39K volatile package is programmed through
Cypress’s CYDH2200E CPLD Boot PROM Programming Kit
via a two-wire interface. For more information on how to pro-
gram the CPLD boot EEPROM, please refer to the data sheet
titled “CYDH2200E CPLD Boot PROM Programming Kit.” For
more information on the architecture and timing specification
of the boot EEPROM, refer to the data sheet titled “CPLD Boot
EEPROM.”
Third-Party Programmers
Cypress support is available on a wide variety of third-party
programmers. All major programmers (including BP Micro,
System General, Hi-Lo) support the Delta39K family.
Development Software Support
Warp
Warp is a state-of-the-art design environment for designing
with Cypress programmable logic. Warp utilizes a subset of
Figure 11. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCLK
相关PDF资料 |
PDF描述 |
|---|---|
| CY39050Z208-222NC | LOADABLE PLD, 7 ns, PQFP208 |
| CY39050Z256-222BBC | LOADABLE PLD, 7 ns, PBGA256 |
| CY39050Z388-222MGC | LOADABLE PLD, 7 ns, PBGA388 |
| CY39050Z484-222MBC | LOADABLE PLD, 7 ns, PBGA484 |
| CY39200V208-167NTC | LOADABLE PLD, 8.5 ns, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39050Z208-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z208-125BBI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z208-125BGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z208-125BGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z388-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
发布紧急采购，3分钟左右您将得到回复。