参数资料
型号: CY39050V484-222MBC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: PLD
英文描述: LOADABLE PLD, 7 ns, PBGA484
封装: 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484
文件页数: 7/57页
文件大小: 1166K
代理商: CY39050V484-222MBC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 15 of 57
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware De-
scription Language (HDL) for design entry. Warp accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Delta39K device. For simulation, Warp provides a graphical
waveform simulator as well as VHDL and Verilog Timing Mod-
els.
VHDL and Verilog are open, powerful, non-proprietary Hard-
ware Description Languages (HDLs) that are standards for be-
havioral design entry and simulation. HDL allows designers to
learn a single language that is useful for all facets of the design
process.
Third-Party Software
Cypress products are supported in a number of third-party de-
sign entry and simulation tools. Refer to the third-party soft-
ware data sheet or contact your local sales office for a list of
currently supported third party vendors.
相关PDF资料
PDF描述
CY39050Z208-222NC LOADABLE PLD, 7 ns, PQFP208
CY39050Z256-222BBC LOADABLE PLD, 7 ns, PBGA256
CY39050Z388-222MGC LOADABLE PLD, 7 ns, PBGA388
CY39050Z484-222MBC LOADABLE PLD, 7 ns, PBGA484
CY39200V208-167NTC LOADABLE PLD, 8.5 ns, PQFP208
相关代理商/技术参数
参数描述
CY39050Z208-125BBC 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050Z208-125BBI 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050Z208-125BGC 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050Z208-125BGI 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39050Z388-125BBC 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities