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参数资料
| 型号： | CY39050Z484-222MBC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 7 ns, PBGA484 |
| 封装： | 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484 |
| 文件页数： | 14/57页 |
| 文件大小： | 1166K |
| 代理商： | CY39050Z484-222MBC |
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PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 21 of 57
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
Cluster memory access time. Delay from address change to read data out
tCLMPWE
Write Enable pulse width
tCLMSA
Address set-up to the beginning of Write Enable with both signals from the same I/O block
tCLMHA
Address hold after the end of Write Enable with both signals from the same I/O block
tCLMSD
Data set-up to the end of Write Enable
tCLMHD
Data hold after the end of Write Enable
Synchronous Mode Parameters
tCLMCYC1
Clock cycle time for flow through read and write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
tCLMCYC2
Clock cycle time for pipelined read and write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCLMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCLMDV1
Global clock to data valid on output pins for flow through data
tCLMDV2
Global clock to data valid on output pins for pipelined data
tCLMMACS1
Cluster memory input clock to macrocell clock in the same cluster
tCLMMACS2
Cluster memory output clock to macrocell clock in the same cluster
tMACCLMS1
Macrocell clock to cluster memory input clock in the same cluster
tMACCLMS2
Macrocell clock to cluster memory output clock in the same cluster
Internal Parameters
tCLMCLAA
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
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| CY39200V208-167NTC | LOADABLE PLD, 8.5 ns, PQFP208 |
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| CY39200V484-167BBC | LOADABLE PLD, 8.5 ns, PBGA484 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39050Z676-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z676-125BBI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z676-125BGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z676-125BGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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