参数资料
型号: CY7C09569V-100AC
英文描述: SYNC SRAM|16KX36|CMOS|QFP|144PIN|PLASTIC
中文描述: 同步静态存储器| 16KX36 |的CMOS | QFP封装| 144Pin支持|塑料
文件页数: 3/20页
文件大小: 301K
代理商: CY7C09569V-100AC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 11 of 20
Notes:
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS
tHD
DATAIN VALID
DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA
tPWE
tSWRD
tDOE
WRITE CYCLE
READ CYCLE
OE
R/W
I/O 0
SEM
A 0–A 2
Semaphore Read After Write Timing, Either Side[37]
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A 0R–A2R
R/WR
SEM R
Timing Diagram of Semaphore Contention[38, 39, 40]
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