参数资料
型号: CY7C1472BV25-250BZXI
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 4M X 18 ZBT SRAM, 3 ns, PBGA165
封装: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
文件页数: 1/29页
文件大小: 884K
代理商: CY7C1472BV25-250BZXI
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL Architecture
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 001-15032 Rev. *D
Revised February 29, 2008
Features
Pin-compatible and functionally equivalent to ZBT
Supports 250 MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
Single 2.5V power supply
2.5V IO supply (VDDQ)
Fast clock-to-output times
3.0 ns (for 250-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1470BV25, CY7C1472BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV25
available in Pb-free and non-Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG Boundary Scan compatible
Burst capability—linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst
SRAMs with No Bus Latency (NoBL
) logic, respectively.
They are designed to support unlimited true back-to-back read
or write operations with no wait states. The CY7C1470BV25,
CY7C1472BV25, and CY7C1474BV25 are equipped with the
advanced (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent read or write transitions. The
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWd
for
CY7C1470BV25,
BWa–BWb
for
CY7C1472BV25, and BWa–BWh for CY7C1474BV25) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
3.0
3.4
ns
Maximum Operating Current
450
400
mA
Maximum CMOS Standby Current
120
mA
相关PDF资料
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CY7C164-15PC 16K x 4 Static RAM
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相关代理商/技术参数
参数描述
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CY7C1472BV33-167ZXI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1472BV33-200AXC 功能描述:静态随机存取存储器 4Mx18,3.3V NoBL PL 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray