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参数资料
| 型号： | DAC1221EG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 1800 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封装： | GREEN, SSOP-16 |
| 文件页数： | 16/16页 |
| 文件大小： | 154K |
| 代理商： | DAC1221EG4 |
9
DAC1221
CALPIN (Calibration Pin) Bit—The CALPIN bit deter-
mines if the output is isolated or connected during calibration.
CRST
0
OFF (default)
1
Reset
CRST (Calibration Reset) Bit—The CRST bit resets the
offset and full-scale calibration registers, as shown:
Offset Two's
Straight
Complement
Binary
VOUT
DF = 0
DF = 1
(default)
8000
0000
0
0000
8000
VREF
7FFF
FFFF
2 VREF
Input Code
DISF (Disable Fast Settling) Bit—The DISF bit disables
the fast settling option. If this bit is zero the fast settling
performance is determined by the ADPT bit.
DISF
0
Fast Settling (default)
1
Disable Fast Settling
BD (Byte Order) Bit—The BD bit controls the order in
which bytes of data are transferred (either most significant
byte first (MSBF) or least significant byte first (LSBF)), as
shown:
BD bit:
0 (default)
1
0 (default)
1
register
INSR
write only
MSBF
CMR
MSBF
LSBF
MSBF
DIR
MSBF
LSBF
MSBF
LSBF
OCR
MSBF
LSBF
MSBF
LSBF
FCR
MSBF
LSBF
MSBF
LSBF
read
write
Care must be observed in reading the Command Register if
the state of the BD bit is unknown. If a two byte read is
started at address 0100 with BD = 0, it will read 0100, then
0101. However, if BD = 1, it will read 0100, then 0011. If
the BD bit is unknown, all reads of the command register are
best performed as read commands of one byte.
MSB (Bit Order) Bit—The MSB bit controls the order in
which bits within a byte of data are read or written (either
most significant bit first or least significant bit first), as
follows:
MD1
MD0
0
Normal Mode
0
1
Self-Cal
1
0
Sleep (default)
1
Reserved
MSB
0
MSB First (default)
1
LSB First
MD1 – MD0 (Operating Mode) Bits—The Operating
Mode bits control the calibration functions of the DAC1221.
The Normal Mode is used to perform conversions. The Self-
Calibration Mode is a one-step calibration sequence that
calibrates both the offset and full scale.
Offset Calibration Register (OCR)
The OCR is a 24-bit register containing the offset correction
factor that is used to apply a correction to the digital input
before it is transferred to the modulator. The results of the
self-calibration process will be written to this register.
The OCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate calibration,
a calibration can be performed, the results averaged, and a
more precise offset calibration value written back to the
OCR.
The actual OCR value will change from part to part and with
configuration, temperature, and power supply.
In addition, be aware that the contents of the OCR are not
used to directly correct the digital input. Rather, the correc-
tion is a function of the OCR value. This function is linear
and two known points can be used as a basis for interpolat-
ing intermediate values for the OCR.
The results of calibration are averaged, Offset Two's Comple-
ment adjusted, and placed in the OCR.
CALPIN
0
Output Isolated (default)
1
Output Connected
CLR (Clear) Bit—The CLR bit synchronously resets the
data input register to zero. The analog output will be based
on the DF bit—if 1, the output will be 0V; if 0, the output
will be VREF.
DF (Data Format) Bit—The DF bit controls the format of
the input data, shown in hexadecimal (either Offset Two’s
Complement or Straight Binary), as shown:
MSB
Byte 2
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
Byte 1
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR9
OCR8
Byte 0
LSB
OCR7
OCR6
OCR5
OCR4
OCR3
OCR2
OCR1
OCR0
TABLE V. Offset Calibration Register.
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