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参数资料
| 型号： | DAC5674EVM |
| 厂商： | Texas Instruments |
| 文件页数： | 11/39页 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR DAC5674 |
| 产品培训模块： | Data Converter Basics |
| 标准包装： | 1 |
| 系列： | CommsDAC™ |
| DAC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 400M |
| 数据接口： | 并联 |
| 设置时间： | 20ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | DAC5674 |
| 相关产品： | DAC5674IPHPRG4-ND - IC DAC 14BIT 400MSPS 48-HTQFP DAC5674IPHPR-ND - IC DAC 14BIT 400MSPS 48-HTQFP DAC5674IPHPG4-ND - IC DAC 14BIT 400MSPS 48-HTQFP 296-15726-ND - IC DAC 14BIT 400MSPS 48-HTQFP |
| 其它名称： | 296-30860 DAC5674EVM-ND |
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DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
19
080
IF=32
160
240
320
112
208
0
100
IF=40
200
300
400
260
140
065
IF=26
130
195
260
91
169
”Sinx/x”
Attenuation
Fupdate+65 MSPS
*1.83 dB
*7.2 dB
”Sinx/x”
Attenuation
Fupdate+80 MSPS
*1.83 dB
*7.2 dB
”Sinx/x”
Attenuation
Fupdate+100 MSPS
*1.83 dB
*7.2 dB
Figure 20. High-Pass 4
y Interpolation Filter Operation: Example Frequencies
Clock Generation Function
An internal phase-locked loop (PLL) or external clock can be used to derive the internal clocks (1
×, 2×, and 4×)
for the logic, FIR interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal
PLL blocks (PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and
CLKGND), thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock
mode: when PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode
is active.
In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes
the 4
× clock and is twice divided down to generate the 2× and 1× clocks. The 2× or 1× clock is multiplexed out
on the PLLLOCK pin to allow for external clock synchronization.
In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four
phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and
drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing
the VCO output by 1
×, 2×, 4×, or 8×, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the
4
× clock, and is divided down twice to generate the 2× and 1× clocks. Pin X4 selects the 1× or 2× clock to clock
in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an
output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user
at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the
clock configurations with corresponding data rate ranges.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DAC5674IPHP | 功能描述:数模转换器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5674IPHPG4 | 功能描述:数模转换器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5674IPHP-ND | 制造商: 功能描述: 制造商:undefined 功能描述: |
| DAC5674IPHPR | 功能描述:数模转换器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5674IPHPRG4 | 功能描述:数模转换器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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