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参数资料
| 型号： | DAC7554IDGSR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 18/23页 |
| 文件大小： | 1224K |
| 代理商： | DAC7554IDGSR |
www.ti.com
TIMING CHARACTERISTICS
(1) (2)
SCLK
SYNC
DIN
LD1
LD0
SEL1
SEL0
D11
D1
D0
X
t8
t4
t3
t2
t1
t7
t6
t5
DAC7554
SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004
V
DD = 2.7 V to 5.5 V, RL = 2 k to GND; all specifications –40°C to 105°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 2.7 V to 3.6 V
20
t1(3)
SCLK cycle time
ns
VDD = 3.6 V to 5.5 V
20
VDD = 2.7 V to 3.6 V
10
t2
SCLK HIGH time
ns
VDD = 3.6 V to 5.5 V
10
VDD = 2.7 V to 3.6 V
10
t3
SCLK LOW time
ns
VDD = 3.6 V to 5.5 V
10
VDD = 2.7 V to 3.6 V
4
SYNC falling edge to SCLK falling edge setup
t4
ns
time
VDD = 3.6 V to 5.5 V
4
VDD = 2.7 V to 3.6 V
5
t5
Data setup time
ns
VDD = 3.6 V to 5.5 V
5
VDD = 2.7 V to 3.6 V
4.5
t6
Data hold time
ns
VDD = 3.6 V to 5.5 V
4.5
VDD = 2.7 V to 3.6 V
0
t7
SCLK falling edge to SYNC rising edge
ns
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
20
t8
Minimum SYNC HIGH time
ns
VDD = 3.6 V to 5.5 V
20
(1)
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
See Serial Write Operation timing diagram Figure 1.
(3)
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
Figure 1. Serial Write Operation
4
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