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参数资料
| 型号： | DAC7554IDGSR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 9/23页 |
| 文件大小： | 1224K |
| 代理商： | DAC7554IDGSR |
www.ti.com
Generating
±5-V, ±10-V, and ± 12-V Outputs For
INTEGRAL AND DIFFERENTIAL LINEARITY
GLITCH ENERGY
CHANNEL-TO-CHANNEL CROSSTALK
APPLICATION INFORMATION
Waveform Generation
DAC7554
SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004
The SYNC input is a level-triggered input that acts as
can exceed 1 MSPS if the waveform to be generated
a frame synchronization signal and chip enable. Data
consists of small voltage steps between consecutive
can only be transferred into the device while SYNC is
DAC updates. To obtain a high dynamic range,
low. To start the serial data transfer, SYNC should be
REF3140 (4.096 V) or REF02 (5.0 V) are rec-
taken low, observing the minimum SYNC to SCLK
ommended for reference voltage generation.
falling edge setup time, t4. After SYNC goes low,
serial data is shifted into the device's input shift
Precision Industrial Control
register on the falling edges of SCLK for 16 clock
pulses. Any data and clock pulses after the sixteenth
Industrial control applications can require multiple
falling edge of SCLK are ignored. No further serial
feedback loops consisting of sensors, ADCs, MCUs,
data transfer occurs until SYNC is taken high and low
DACs, and actuators. Loop accuracy and loop speed
again.
are the two important parameters of such control
loops.
SYNC may be taken high after the falling edge of the
sixteenth SCLK pulse, observing the minimum SCLK
Loop Accuracy:
falling edge to SYNC rising edge time, t7.
In a control loop, the ADC has to be accurate. Offset,
After the end of serial data transfer, data is automati-
gain, and the integral linearity errors of the DAC are
cally transferred from the input shift register to the
not factors in determining the accuracy of the loop.
input register of the selected DAC. If SYNC is taken
As long as a voltage exists in the transfer curve of a
high before the sixteenth falling edge of SCLK, the
monotonic DAC, the loop can find it and settle to it.
data transfer is aborted and the DAC input registers
On the other hand, DAC resolution and differential
are not updated.
linearity do determine the loop accuracy, because
each DAC step determines the minimum incremental
change the loop can generate. A DNL error less than
–1 LSB (non-monotonicity) can create loop instability.
The DAC7554 uses precision thin-film resistors pro-
A DNL error greater than +1 LSB implies unnecess-
viding exceptional linearity and monotonicity. Integral
arily large voltage steps and missed voltage targets.
linearity error is typically within (+/-) 0.35 LSBs, and
With high DNL errors, the loop looses its stability,
differential linearity error is typically within (+/-) 0.08
resolution, and accuracy. Offering 12-bit ensured
LSBs.
monotonicity and
± 0.08 LSB typical DNL error, 755X
DACs are great choices for precision control loops.
Loop Speed:
The DAC7554 uses a proprietary architecture that
minimizes glitch energy. The code-to-code glitches
Many factors determine control loop speed. Typically,
are so low, they are usually buried within the
the ADC's conversion time, and the MCU's compu-
wide-band noise and cannot be easily detected. The
tation time are the two major factors that dominate
DAC7554 glitch is typically well under 0.1 nV-s. Such
the time constant of the loop. DAC settling time is
low glitch energy provides more than 10X improve-
rarely a dominant factor because ADC conversion
ment over industry alternatives.
times usually exceed DAC conversion times. DAC
offset, gain, and linearity errors can slow the loop
down only during the start-up. Once the loop reaches
its steady-state operation, these errors do not affect
The DAC7554 architecture is designed to minimize
loop speed any further. Depending on the ringing
channel-to-channel crosstalk. The voltage change in
characteristics of the loop's transfer function, DAC
one channel does not affect the voltage output in
glitches can also slow the loop down. With its 1
another channel. The DC crosstalk is in the order of a
MSPS (small-signal) maximum data update rate,
few microvolts. AC crosstalk is also less than –100
DAC7554 can support high-speed control loops.
dBs. This provides orders of magnitude improvement
Ultra-low glitch energy of the DAC7554 significantly
over certain competing architectures.
improves loop stability and loop settling time.
Generating Industrial Voltage Ranges:
For control loop applications, DAC gain and offset
errors are not important parameters. This could be
Due to its exceptional linearity, low glitch, and low
exploited to lower trim and calibration costs in a
crosstalk, the DAC7554 is well suited for waveform
high-voltage control circuit design. Using a quad
generation (from DC to 10 kHz). The DAC7554
operational amplifier (OPA4130), and a voltage refer-
large-signal settling time is 5 s, supporting an
ence (REF3140), the DAC7554 can generate the
update rate of 200 KSPS. However, the update rates
wide voltage swings required by the control loop.
17
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| DAC7558EVM | 功能描述:数据转换 IC 开发工具 DAC7558 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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| DAC7558IRHBRG4 | 功能描述:数模转换器- DAC 12-Bit Octal UltrLo Glitch Vltg Output RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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