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参数资料
| 型号： | DC1009A-A |
| 厂商： | Linear Technology |
| 文件页数： | 26/36页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2492 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1009A Design File DC1009A Schematic |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2492 |
| 已供物品： | 板 |
| 相关产品： | LTC2492CDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492IDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492IDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492CDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN |
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LTC2492
32
2492fd
APPLICATIONS INFORMATION
Using the 2x speed mode of the LTC2492 alters the rejection
characteristics around DC and multiples of fS. The device
bypasses the offset calibration in order to increase the
output rate. The resulting rejection plots are shown in
Figures 27 and 28. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results (see Figure 29).
Output Data Rate
When using its internal oscillator, the LTC2492 produces up
to 7.5 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignicantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2492 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSCoverthenominal307.2kHzwilltranslate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and
effective resolution as well as a shift in frequency rejection.
When using the integrated temperature sensor, the internal
oscillator should be used or an external oscillator, fEOSC =
307.2kHz maximum.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased
above 1MHz (a more than 3x increase in output rate) the
effectiveness of internal auto calibration circuits begins
to degrade. This results in larger offset errors, full scale
errors, and decreased resolution (see Figures 30 to 37).
INPUT SIGNAL FREQUENCY (fN)
INPUT
NORMAL
REJECTION
(dB)
2492 F27
0
–20
–40
–60
–80
–100
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN 8fN
Figure 27. Input Normal Mode Rejection 2x Speed Mode
INPUT SIGNAL FREQUENCY (fN)
INPUT
NORMAL
REJECTION
(dB)
2492 F28
0
–20
–40
–60
–80
–100
–120
250
248
252 254 256 258 260 262 264
Figure 28. Input Normal Mode Rejection 2x Speed Mode
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