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参数资料
| 型号： | DC1009A-A |
| 厂商： | Linear Technology |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2492 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1009A Design File DC1009A Schematic |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2492 |
| 已供物品： | 板 |
| 相关产品： | LTC2492CDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492IDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492IDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492CDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN |
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LTC2492
17
2492fd
APPLICATIONS INFORMATION
Bit 28 (fourth output bit) is the most signicant bit (MSB)
of the result. This bit in conjunction with Bit 29 also pro-
vides underrange and overrange indication. If both Bit 29
and Bit 28 are HIGH, the differential input voltage is above
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2492 Status Bits
INPUT RANGE
BIT 31
EOC
BIT 30
DMY
BIT 29
SIG
BIT 28
MSB
VIN ≥ 0.5 VREF
0011
0V ≤ VIN < 0.5 VREF
0
1/0
0
–0.5 VREF ≤ VIN < 0V
0001
VIN < –0.5 VREF
0000
Bits 28 to 5 are the 24-bit conversion result MSB rst.
Bit 5 is the least signicant bit (LSB24).
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the fO pin from HIGH to LOW at the completion
of a conversion. This signal may be used as an interrupt for
an external microcontroller. Bit 31 (EOC) can be captured
on the rst rising edge of SCK. Bit 30 is shifted out of the
device on the rst falling edge of SCK. The nal data bit
(Bit 0) is shifted out on the on the falling edge of the 31st
SCK and may be latched on the rising edge of the 32nd SCK
pulse. On the falling edge of the 32nd SCK pulse, SDO goes
HIGH indicating the initiation of a new conversion cycle.
This bit serves as EOC (Bit 31) for the next conversion
cycle. Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum
operating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
–FS – 1LSB.
INPUT DATA FORMAT
The LTC2492 serial input word is 13 bits long and contains
two distinct sets of data. The rst set (SGL, ODD, A2, A1, A0)
is used to select the input channel. The second set of data
(IM, FA, FB, SPD) is used to select the frequency rejection,
speed mode (1
×, 2×), and temperature measurement.
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 to CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1
× output rate (auto-calibration enabled). The rst
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2492 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
SIG
BIT 29
“0”
BIT 30
BIT 31
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
BIT 18 BIT 17
BIT 0
12
3
4
5
6
7
8
9
10
11
12
13
14
32
DON'T CARE
Figure 3. Channel Selection, Conguration Selection and Data Output Timing
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