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参数资料
| 型号： | DC1009A-A |
| 厂商： | Linear Technology |
| 文件页数： | 8/36页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2492 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1009A Design File DC1009A Schematic |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2492 |
| 已供物品： | 板 |
| 相关产品： | LTC2492CDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492IDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492IDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN LTC2492CDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN |
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LTC2492
16
2492fd
APPLICATIONS INFORMATION
SERIAL INTERFACE PINS
The LTC2492 transmits the conversion result, reads the
input conguration, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface
can be used to access the converter status. During the
data output state, it is used to read the conversion result,
program the input channel, rejection frequency, speed
multiplier, and select the temperature sensor.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be congured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply oating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Specic
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB rst) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW, EOC will
be driven LOW indicating the conversion is complete and
the result is ready to be shifted out of the device.
Chip Select (
CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 32 data bits read) or by pulling
CS HIGH any time between the rst and 32nd rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input chan-
nel, rejection frequency, speed multiplier and to access
the integrated temperature sensor. Data is shifted into the
device during the data output/input state on the rising edge
of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2492 serial output stream is 32 bits long. The
rst bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 24 bits are the conversion result, MSB rst. The
remaining 5 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (rst output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This bit
is HIGH during the conversion cycle, goes LOW once the
conversion is complete, and is Hi-Z when CS is HIGH.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indica-
tor (SIG). If the selected input (VIN = IN+ – IN–) is greater
than 0V, this bit is HIGH. If VIN < 0, this bit is LOW.
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