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参数资料
| 型号： | DC1082A-F |
| 厂商： | Linear Technology |
| 文件页数： | 5/18页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2355-14 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1082A Design File DC1082A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 3M |
| 数据接口： | 串行，SPI? |
| 输入范围： | 0 ~ 2.5 V |
| 已用 IC / 零件： | LTC2355-14 |
| 已供物品： | 板 |
| 相关产品： | LTC2355IMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355IMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355IMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355IMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355CMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP |
LTC2355-12/LTC2355-14
2355fa
applications inFormation
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2355-12/LTC2355-14, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the first page of this data sheet. For
optimum performance, a 10F surface mount Tantalum
capacitor with a 0.1F ceramic is recommended for the
VDDandVREFpins.Alternatively,10Fceramicchipcapaci-
Figure 5. Recommended Layout
tors such as Murata GRM235Y5V106Z016 may be used.
The capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as
wide as possible.
Figure5showstherecommendedsystemgroundconnec-
tions. All analog circuitry grounds should be terminated
at the LTC2355-12/LTC2355-14 GND (Pins 4, 5, 6 and
exposed pad). The ground return from the LTC2355-
12/LTC2355-14 (Pins 4, 5, 6 and exposed pad) to the
power supply should be low impedance for noise free
operation. In applications where the ADC data outputs
and control signals are connected to a continuously ac-
tive microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
POWER-DOWN MODES
Upon power-up, the LTC2355-12/LTC2355-14 is initial-
ized to the active state and is ready for conversion.
The Nap and Sleep mode waveforms show the power-
down modes for the LTC2355-12/LTC2355-14. The SCK
and CONV inputs control the power-down modes (see
Timing Diagrams). Two rising edges at CONV, without
any intervening rising edges at SCK, put the LTC2355-
12/LTC2355-14 in Nap mode and the power consumption
dropsfrom18mWto4mW.Theinternalreferenceremains
powered in Nap mode. One or more rising edges at SCK
wake up the LTC2355-12/LTC2355-14 very quickly, and
CONV can start an accurate conversion within a clock
cycle. Four rising edges at CONV, without any interven-
ing rising edges at SCK, put the LTC2355-12/LTC2355-14
VREF BYPASS 0805 SIZE
VDD BYPASS 0805 SIZE
OPTIONAL INPUT FILTERING
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