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参数资料
| 型号： | DC1082A-F |
| 厂商： | Linear Technology |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2355-14 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1082A Design File DC1082A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 3M |
| 数据接口： | 串行，SPI? |
| 输入范围： | 0 ~ 2.5 V |
| 已用 IC / 零件： | LTC2355-14 |
| 已供物品： | 板 |
| 相关产品： | LTC2355IMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355IMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355IMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355IMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355CMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP |
LTC2355-12/LTC2355-14
2355fa
applications inFormation
in Sleep mode and the power consumption drops from
18mW to 13W. One or more rising edges at SCK wake
up the LTC2355-12/LTC2355-14 for operation. The inter-
nal reference (VREF ) takes 2ms to slew and settle with a
10F load. Note that, using sleep mode more frequently
than every 2ms, compromises the settled accuracy of the
internal reference. Note that, for slower conversion rates,
the Nap and Sleep modes can be used for substantial
reductions in power consumption.
DIGITAL INTERFACE
The LTC2355-12/LTC2355-14 has a 3-wire SPI-compatible
(Serial Protocol Interface) interface. The SCK and CONV
inputs and SDO output implement this interface. The SCK
and CONV inputs accept swings from 3.3V logic and are
TTL compatible, if the logic swing does not exceed VDD.
A detailed description of the three serial port signals fol-
lows.
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but
subsequent rising edges at CONV are ignored by the
LTC2355-12/LTC2355-14 until the following 16 SCK rising
edges have occurred. It is necessary to have a minimum
of 16 rising edges of the clock input SCK between rising
edges of CONV. But to obtain maximum conversion speed
(witha63MHzSCK),itisnecessarytoallowtwomoreclock
periods between conversions to allow 39ns of acquisition
time for the internal ADC sample-and-hold circuit. With 16
clock periods per conversion, the maximum conversion
rate is limited to 3.5Msps to allow 39ns for acquisition
time. In either case, the output data stream comes out
within the first 16 clock periods to ensure compatibility
with processor serial ports. The duty cycle of CONV can
be arbitrarily chosen to be used as a frame sync signal for
the processor serial port. A simple approach to generate
CONV is to create a pulse that is one SCK wide to drive the
LTC2355-12/LTC2355-14 and then buffer this signal with
the appropriate number of inverters to ensure the correct
delay driving the frame sync input of the processor serial
port. It is good practice to drive the LTC2355-12/LTC2355-
14 CONV input first to avoid digital noise interference
during the sample-to-hold transition triggered by CONV
at the start of conversion. It is also good practice to keep
the width of the low portion of the CONV signal greater
than 15ns to avoid introducing glitches in the front end of
the ADC just before the sample-and-hold goes into hold
mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
Inhighspeedapplicationswherehighamplitudesinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement. The challenge is to generate a CONV
signalfromthiscrystalclockwithoutjittercorruptionfrom
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in Figure 6, the
SCK and CONV inputs should be driven first, with digital
buffers used to drive the serial port interface. Also note
that the master clock in the DSP may already be corrupted
with jitter, even if it comes directly from the DSP crystal.
Another problem with high speed processor clocks is that
they often use a low cost, low speed crystal (i.e., 10MHz)
to generate a fast, but jittery, phase-locked-loop system
clock (i.e., 40MHz). The jitter in these PLL-generated high
speed clocks can be several nanoseconds. Note that if
you choose to use the frame sync signal generated by
the DSP port, this signal will have the same jitter of the
DSP’s master clock.
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