参数资料
型号: DC1096A
厂商: Linear Technology
文件页数: 20/24页
文件大小: 0K
描述: BOARD DAC LTC2642-16
软件下载: QuikEval System
设计资源: DC1096A Design File
DC1096A Schematic
标准包装: 1
系列: QuikEval™
DAC 的数量: 1
位数: 16
数据接口: MICROWIRE?,QSPI?,串行,SPI?
设置时间: 1µs
DAC 型: 电压
工作温度: 0°C ~ 70°C
已供物品:
已用 IC / 零件: LTC2642-16
LTC2641/LTC2642
5
26412fc
For more information www.linear.com/LTC2641
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale.
LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale.
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IIN
Digital Input Current
VIN = GND to VDD
l
±1
A
CIN
Digital Input Capacitance
(Note 6)
l
3
10
pF
VH
Hysteresis Voltage
0.15
V
Power Supply
VDD
Supply Voltage
l
2.7
5.5
V
IDD
Supply Current, VDD
Digital Inputs = 0V or VDD
l
120
200
A
PD
Power Dissipation
Digital Inputs = 0V or VDD, VDD = 5V
Digital Inputs = 0V or VDD, VDD = 3V
0.60
0.36
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
DIN Valid to SCLK Setup Time
l
10
ns
t2
DIN Valid to SCLK Hold Time
l
0
ns
t3
SCLK Pulse Width High
l
9
ns
t4
SCLK Pulse Width Low
l
9
ns
t5
CS Pulse High Width
l
10
ns
t6
LSB SCLK High to CS High
l
8
ns
t7
CS Low to SCLK High
l
8
ns
t8
CS High to SCLK Positive Edge
l
8
ns
t9
CLR Pulse Width Low
l
15
ns
fSCLK
SCLK Frequency
50% Duty Cycle
l
50
MHz
VDD High to CS Low (Power-Up Delay)
30
s
Note 4: ROUT tolerance is typically ±20%.
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
tested.
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