参数资料
型号: DC1096A
厂商: Linear Technology
文件页数: 3/24页
文件大小: 0K
描述: BOARD DAC LTC2642-16
软件下载: QuikEval System
设计资源: DC1096A Design File
DC1096A Schematic
标准包装: 1
系列: QuikEval™
DAC 的数量: 1
位数: 16
数据接口: MICROWIRE?,QSPI?,串行,SPI?
设置时间: 1µs
DAC 型: 电压
工作温度: 0°C ~ 70°C
已供物品:
已用 IC / 零件: LTC2642-16
LTC2641/LTC2642
11
26412fc
For more information www.linear.com/LTC2641
operaTion
TiMing DiagraM
General Description
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
±1LSB integral linearity error and less than ±1LSB differ-
ential linearity error, guaranteeing monotonic operation.
They operate from a single supply ranging from 2.7V to
5.5V, consuming 120A (typical). An external voltage
reference of 2V to VDD determines the DAC’s full-scale
output voltage. A 3-wire serial interface allows the
LTC2641/LTC2642 to fit into a small 8-/10-pin MSOP or
DFN 3mm
× 3mm package.
Digital-to-Analog Architecture
The DAC architecture is a voltage switching mode resis-
tor ladder using precision thin-film resistors and CMOS
switches. The LTC2641/LTC2642 DAC resistor ladders are
composed of a proprietary arrangement of matched DAC
sections. The four MSBs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
impulse is very low at 500pVsec, CL = 10pF, ten times
lower than previous DACs of this type.
The digital-to-analog transfer function at the VOUT pin
is:
VOUT(IDEAL) =
k
2N
VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and VREF is between 2.0V and
VDD (see Tables 1a, 1b and 1c).
The LTC2642 includes matched resistors that are tied
to an external amplifier to provide bipolar output swing
(Figure 2). The bipolar transfer function at the RFB pin is:
VOUT_BIPOLAR(IDEAL) = VREF
k
2N–1
– 1
(see Tables 2a, 2b and 2c).
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
chip select input (CS) controls and frames the loading
of serial data from the data input (DIN). Following a CS
t1
SCK
SDI
CS/LD
t5
t7
t2
t6
t8
26412 TD
1
2
3
15
16
t3
t4
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