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参数资料
| 型号： | DC1453A |
| 厂商： | Linear Technology |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LTM4619 |
| 软件下载： | LTM4619 Spice Model |
| 设计资源： | DC1453A Design Files DC1453A Schematic |
| 标准包装： | 1 |
| 系列： | LTM®, uModule® |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.8V，3.3V |
| 电流 - 输出： | 4A |
| 输入电压： | 4.5 ~ 28 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTM4619 |
| 相关产品： | LTM4619IV#PBF-ND - IC SWIT REG BUCK 4A ADJ 144LGA LTM4619EV#PBF-ND - IC SWIT REG BUCK 4A ADJ 144LGA |
LTM4619
APPLICATIONS INFORMATION
Mode Selections and Phase-Locked Loop
The LTM4619 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency pulse-skipping
mode, or forced continuous conduction mode. To select
the forced continuous operation, tie the MODE/PLLIN pin
to a DC voltage below 0.8V. To select pulse-skipping mode
of operation, tie the MODE/PLLIN pin to INTV CC . To select
Burst Mode operation, float the MODE/PLLIN pin.
Frequency Synchronization
A phase-lock loop is available on the LTM4619 to syn-
chronize the internal clock to an external clock source
connected on the MODE/PLLIN pin. The clock high level
needs to be higher than 1.6V and the clock low level needs
to be lower than 1V. The frequency programming voltage
and or the programming voltage divider must be removed
from the FREQ/PLLFLTR pin when synchronizing to an
external clock. The FREQ/PLLFLTR pin has the required
onboard PLL filter components for clock synchronization.
The LTM4619 will default to forced continuous mode while
being clock synchronized. Channel 1 is synchronized to
the rising edge on the external clock, and channel 2 is 180
degrees out-of-phase with the external clock.
Frequency Selection
The switching frequency of the LTM4619’s controllers
can be selected using the FREQ/PLLFLTR pin. If the
MODE/PLLIN pin is not being driven by an external clock
source, the FREQ/PLLFLTR pin can be set from 0V to 2.4V to
program the controller’s operating frequency from 250kHz
to 780kHz using a voltage divider to INTV CC (see Figure
19). The typical frequency is 780kHz. If the output is too
low or the minimum on-time is reached, the frequency
needs to decrease to enlarge the turn-on time. Otherwise,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
900
800
700
600
500
400
300
200
100
0
0 0.5 1 1.5 2 2.5
FREQ/PLLFLTR PIN VOLTAGE (V)
4619 F02
Figure 2. Switching Frequency vs FREQ/PLLFLTR Pin Voltage
4619fb
10
For more information www.linear.com/LTM4619
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