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参数资料
| 型号： | DC570A |
| 厂商： | Linear Technology |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2440 |
| 软件下载： | QuikEval System |
| 设计资源： | DC570A Design File DC570A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 3.5k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2440 |
| 已供物品： | 板 |
| 相关产品： | LTC2440CGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440CGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440IGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP |
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LTC2440
19
2440fd
APPLICATIONS INFORMATION
Figure 10. Internal Serial Clock, Continuous Operation
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the rst rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ltering. Combined
with a large oversampling ratio, the LTC2440 signicantly
simplies antialiasing lter requirements.
The LTC2440’s speed/resolution is determined by the
over sample ratio (OSR) of the on-chip digital lter. The
OSR ranges from 64 for 3.5kHz output rate to 32,768
for 6.9Hz output rate. The value of OSR and the sample
rate fS determine the lter characteristics of the device.
The rst NULL of the digital lter is at fN and multiples
of fN where fN = fS/OSR, see Figure 11 and Table 5. The
rejection at the frequency fN ±14% is better than 80dB,
see Figure 12.
If fO is grounded, fS is set by the on-chip oscillator at
1.8MHz ±5% (over supply and temperature variations). At
an OSR of 32,768, the rst NULL is at fN = 55Hz and the
no latency output rate is fN/ 8 = 6.9Hz. At the maximum
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
SDO
BUSY
SCK
(INTERNAL)
CS
LSB24
MSB
SIG
BIT 5
BIT 0
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2410 F10
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–
SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
4
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
VCC
7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
2-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
180
2440 F11
–80
–100
60
120
240
–120
–140
–20
NORMAL
MODE
REJECTION
(dB)
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